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David R Kaeli, 6577 Spring Park Ave #2, Boston, MA 02130

Known as:
David D Kaeli Davie Kaeli Dorothy Kaeli

David Kaeli Phones & Addresses

77 Spring Park Ave #2, Jamaica Plain, MA 02130    508-5339128   

Boston, MA   

Rhinebeck, NY   

7 Puddingstone Ln, Medway, MA 02053    508-5339128   

Maynard, MA   

Livingston, NJ   

Ramsey, NJ   

7 Puddingstone Ln, Medway, MA 02053    508-6312214   

Work

Position: Financial Professional

Education

Degree: Associate degree or higher
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David Kaeli resumes & CV records

Resumes

David Kaeli Photo 15

Professor Of Electrical And Computer Engineering

Location:
77 Spring Park Ave, Boston, MA 02130
Industry:
Higher Education
Work:
Northeastern University since Sep 1993
Professor of Electrical and Computer Engineering Northeastern University - College of Engineering Jul 2010 - Jun 2013
Associate Dean of Undergraduate Programs Akorri 2005 - 2011
Consultant IBM TJ Watson Research Center 1986 - 1993
Engineer IBM Sep 1981 - Jul 1993
Advisory Engineer
Education:
Rutgers, The State University of New Jersey-New Brunswick 1987 - 1992
PhD, Electrical Engineering Syracuse University 1981 - 1985
MS, Computer Engineering Rutgers, The State University of New Jersey-New Brunswick 1977 - 1981
BS, Electrical Engineering
Skills:
Computer Architecture, Distributed Systems, Parallel Computing, Algorithms, C++, C, High Performance Computing, Matlab, Machine Learning, Computer Science, Programming, Simulations, Python, Signal Processing, Scientific Computing, Linux, Embedded Systems, Latex, Gpgpu, Software Development, Microprocessors, Image Processing, Perl, Java, Cuda, Vhdl, Mathematical Modeling, Software Engineering, Parallel Programming, Artificial Intelligence, Numerical Analysis, Fortran, Pattern Recognition, Computer Vision, Unix, Mpi, Vlsi, High Performance Computing, Eclipse, Software Design
Interests:
Human Rights
Science and Technology
Children
Environment
David Kaeli Photo 16

Professor At Northeastern University

Position:
Associate Dean of Undergraduate Programs at Northeastern University - College of Engineering, Professor of Electrical and Computer Engineering at Northeastern University
Location:
Greater Boston Area
Industry:
Higher Education
Work:
Northeastern University - College of Engineering since Jul 2010
Associate Dean of Undergraduate Programs Northeastern University since Sep 1993
Professor of Electrical and Computer Engineering Akorri 2005 - 2011
Consultant IBM TJ Watson Research Center 1986 - 1993
Engineer IBM Sep 1981 - Jul 1993
Advisory Engineer
Education:
Rutgers, The State University of New Jersey-New Brunswick 1987 - 1992
PhD, Electrical Engineering Syracuse University 1981 - 1985
MS, Computer Engineering Rutgers, The State University of New Jersey-New Brunswick 1977 - 1981
BS, Electrical Engineering
Skills:
Computer Architecture, Parallel Computing, C, C++, Programming, Distributed Systems, Software Development, Matlab, Python, Fortran, Embedded Systems, Perl, Algorithms, Machine Learning, Java, Pattern Recognition, Eclipse, Computer Vision, Signal Processing, Linux

Publications & IP owners

Us Patents

Resource Flow Computing Device

US Patent:
6976150, Dec 13, 2005
Filed:
Apr 6, 2001
Appl. No.:
09/828600
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F015/173
US Classification:
712 18, 712 26, 712201, 712215
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates

US Patent:
7210025, Apr 24, 2007
Filed:
Apr 19, 2001
Appl. No.:
09/838678
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.

Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates

US Patent:
7380108, May 27, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515220
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
Board of Govenors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.

Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates

US Patent:
7409534, Aug 5, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515374
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.

Concurrent Execution Of Instructions In A Processing System

US Patent:
7991980, Aug 2, 2011
Filed:
Oct 20, 2008
Appl. No.:
12/254684
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 9/30
US Classification:
712217
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Systems And Methods For Determining Placement Of Virtual Machines

US Patent:
8099487, Jan 17, 2012
Filed:
Sep 29, 2010
Appl. No.:
12/893937
Inventors:
George Smirnov - Littleton MA, US
Kenneth Hu - Littleton MA, US
David Kaeli - Littleton MA, US
Assignee:
NetApp, Inc. - Sunnyvale CA
International Classification:
G06F 15/173
G06F 9/455
US Classification:
709223, 709226, 718 1
Abstract:
Systems and methods are provided for determining an optimized placement for a virtual machine in a virtualized environment on the basis of available performance metrics, in which the virtualized environment includes at least two virtual machines, each hosting at least one application, and at least one virtualized hardware system managed by at least one virtualization server.

Not-Taken Path Instruction For Selectively Generating A Forwarded Result From A Previous Instruction Based On Branch Outcome

US Patent:
8601245, Dec 3, 2013
Filed:
Jul 15, 2011
Appl. No.:
13/183662
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 9/30
US Classification:
712226, 712239
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Managing Application System Load

US Patent:
2008002, Jan 31, 2008
Filed:
Jul 5, 2007
Appl. No.:
11/773825
Inventors:
Richard Corley - Littleton MA, US
William Stronge - Littleton MA, US
Kevin Faulkner - Littleton MA, US
Brian Schofer - Littleton MA, US
David Kaeli - Littleton MA, US
Peter Beale - Littleton MA, US
International Classification:
G06F 17/30
US Classification:
707010000
Abstract:
An improvement in a networked digital computing system comprises an Information Resource Manager (IRM) operable to communicate with elements of the digital computing system to obtain performance information regarding operation of and resources available in the computing system, and to utilize this information to enable the IRM to adjust the application parameters relating to application execution, thereby to optimize execution of the at least one application program. The IRM comprises (1) a performance profiling system operable to communicate with the at least one CPU, network and SAN and to obtain therefrom performance information and configuration information, (2) an analytical performance model system, operable to communicate with the performance profiling system and to receive the performance information and configuration information and to utilize the performance information and configuration information to generate an analytical model output, the analytical model output comprising any of performance statistics and updated application parameters, and (3) an application parameter determination system, operable to communicate with the analytical model system, to receive therefrom the analytical model output, to determine, in response to the analytical model output, updated application parameter values, and to transmit the updated application parameter values to at least one application running on the digital computing system, for use by the application to set its application parameters, thereby to optimize execution of multiple applications running on the digital computing system, using updated runtime parameters.

Isbn (Books And Publications)

High Performance Embedded Architectures And Compilers: Second International Conference, Hipeac 2007, Ghent, Belgium, January 28-30, 2007. Proceedings

Author:
David Kaeli
ISBN #:
3540693378

Possible Relatives

David Last  David W Johnson  David Stamps  David L Stanard  David M Stanbery  David A Stanchfield  David J Stanciel  David Stancil  David A Stanczak  David Standen 

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