Calvin E Li, 742815 Van Ness Ave APT 9, San Francisco, CA 94109

6627530, Sep 30, 2003

Dec 22, 2000

09/746204

Calvin K. Li - Fremont CA
N. Johan Knall - Sunnyvale CA
Michael A. Vyvoda - Fremont CA
James M. Cleeves - Redwood City CA
Vivek Subramanian - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

H01L 214763

438622, 438624

The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure. In terms of patterning techniques, a desired edge angle is targeted by modifying, for example, the etch chemistry from one that is generally anisotropic to one that has a horizontal component to achieve an edge angle that is slightly re-entrant (i. e.

6649451, Nov 18, 2003

Feb 2, 2001

09/776000

Michael A. Vyvoda - Fremont CA
James M. Cleeves - Redwood City CA
Calvin K. Li - Fremont CA
Samuel V. Dunton - San Jose CA

Matrix Semiconductor, Inc. - Santa Clara CA

H01L 2182

438128, 438164, 438233, 438586, 438669, 438692, 438787

Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.

6770939, Aug 3, 2004

Sep 26, 2002

10/256116

Vivek Subramanian - Redwood City CA
James M. Cleeves - Redwood City CA
N. Johan Knall - Sunnyvale CA
Calvin K. Li - Fremont CA
Michael A. Vyvoda - Fremont CA

Matrix Semiconductor, Inc. - Santa Clara CA

H01L 2976

257368, 257381, 257390, 257467, 438795

An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

7071565, Jul 4, 2006

Sep 26, 2002

10/255884

Calvin K. Li - Fremont CA, US
N. Johan Knall - Sunnyvale CA, US
Michael A. Vyvoda - Fremont CA, US
James M. Cleeves - Redwood City CA, US
Vivek Subramanian - Redwood City CA, US

Sandisk 3D LLC - Sunnyvale CA

H01L 23/48
H01L 23/52
H01L 29/40
G11C 8/00

257775, 257776, 257758, 365242, 365243

A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

7629247, Dec 8, 2009

Apr 12, 2007

11/786620

Calvin Li - Fremont CA, US
Christopher Petti - Mountain View CA, US

Sandisk 3D LLC - Milpitas CA

H01L 21/4763

438621, 438197, 438700, 257E2117, 257E21051, 257E21227, 257E21229, 257E21304, 257E21315, 257E21267

A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements.

7830028, Nov 9, 2010

Jun 30, 2007

11/772130

Calvin K. Li - Fremont CA, US
Yung-Tin Chen - Santa Clara CA, US
Paul Wai Kie Poon - Fremont CA, US

SanDisk Corporation - Milpitas CA

H01L 23/544

257797, 257E23179, 438401, 438462, 356400, 356401, 716 19, 716 20, 716 21

Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.

7927990, Apr 19, 2011

Jun 29, 2007

11/771137

Calvin K Li - Fremont CA, US
Christopher J Petti - Mountain View CA, US

SanDisk Corporation - Milpitas CA

H01L 21/20

438584, 438381, 438396, 438393, 438253, 438239, 438240, 438626, 257758, 257E21495

A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.

7932157, Apr 26, 2011

Jun 30, 2007

11/772128

Calvin K. Li - Fremont CA, US
Yung-Tin Chen - Santa Clara CA, US
Paul Wai Kie Poon - Fremont CA, US

SanDisk Corporation - Milpitas CA

H01L 21/76

438401, 438 14, 257 48, 257E23179

Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.