Alan Cuthbertson, 65Rocklin, CA

2022029, Sep 22, 2022

Mar 18, 2021

17/206079

- San Jose CA, US
Daesung Lee - San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00
B81B 7/00

A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

2022018, Jun 16, 2022

Dec 10, 2021

17/547388

- San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00

A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.

2023010, Mar 30, 2023

Nov 29, 2022

18/071322

- San Jose CA, US
Daesung Lee - San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00
B81B 7/00

A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electromechanical system (MEMS) device pattern is etched into the device wafer.

2023003, Feb 9, 2023

Jul 29, 2022

17/877089

- San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00

A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.

2023004, Feb 9, 2023

Jul 29, 2022

17/877151

- San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00

A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.

2023004, Feb 9, 2023

Jul 29, 2022

17/877207

- San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81C 1/00
B81B 3/00
B81B 7/00

A device includes a substrate comprising a first standoff, a second standoff, a third standoff, a first cavity, a second cavity, and a bonding material covering a portion of the first, the second, and the third standoff. The first cavity is positioned between the first and the second standoffs, and the second cavity is positioned between the second and the third standoffs. The first cavity comprises a first cavity region and a second cavity region separated by a portion of the substrate extruding thereto, and wherein a depth associated with the first cavity region is greater than a depth associated with the second cavity. A surface of the first cavity is covered with a getter material.

2021010, Apr 15, 2021

Sep 22, 2020

17/028552

- San Jose CA, US
Alan Cuthbertson - San Jose CA, US

B81B 7/00
B81B 3/00
B81C 1/00
G01P 1/00
G01C 19/5712
G01P 15/08

Selective self-assembled monolayer patterning with sacrificial layer for devices is provided herein. A sensor device can include a handle layer and a device layer that comprises a first side and a second side. First portions of the first side are operatively connected to defined portions of the handle layer. At least one area of the second side comprises an anti-stiction area formed with an anti-stiction coating. The device can also include a Complementary Metal-Oxide-Semiconductor (CMOS) wafer operatively connected to second portions of the second side of the device layer. The CMOS wafer comprises at least one bump stop. The anti-stiction area faces the at least one bump stop.

2020026, Aug 20, 2020

Feb 19, 2020

16/795514

- San Jose CA, US
Ian Flader - Redwood City CA, US
Alan Cuthbertson - San Jose CA, US
Emad Mehdizadeh - San Jose CA, US

B81B 3/00
B81C 1/00

Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.