Alexander Minkin resumes & CV records
Resumes
Alexander Minkin
Location:
United States
Alexander Lev Minkin, 631131 Hillslope Pl, Los Altos, CA 94024
Alexander Minkin Phones & Addresses
1131 Hillslope Pl, Los Altos, CA 94024
2042 Crist Dr, Los Altos, CA 94024
Sunnyvale, CA
Santa Clara, CA
800 Charleston Rd, Palo Alto, CA 94303
San Francisco, CA
Royal Oak, MI
Mentions for Alexander Lev Minkin
Publications & IP owners
Us Patents
Circuit And Method For Addressing A Texture Cache
US Patent:
6924811, Aug 2, 2005
Filed:
Nov 13, 2000
Appl. No.:
09/712632
Inventors:
Alexander L. Minkin - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T011/40
US Classification:
345552, 345557, 345568, 345582, 711 3, 711118, 711216
Abstract:
A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate is discussed.
Method And System For Scalable, Dataflow-Based, Programmable Processing Of Graphics Data
US Patent:
6980209, Dec 27, 2005
Filed:
Jun 14, 2002
Appl. No.:
10/172174
Inventors:
Christopher D. S. Donham - San Mateo CA, US
Alexander Lev Minkin - Los Altos CA, US
Bryon Nordquist - San Jose CA, US
Edward A. Hutchins - Mountain View CA, US
Mark Tian - Mountain View CA, US
George Easton Scott III - Dublin CA, US
Alexander Lev Minkin - Los Altos CA, US
Bryon Nordquist - San Jose CA, US
Edward A. Hutchins - Mountain View CA, US
Mark Tian - Mountain View CA, US
George Easton Scott III - Dublin CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T015/50
US Classification:
345426, 345582, 345506
Abstract:
A scalable pipelined pixel shader that processes packets of data and preserves the format of each packet at each processing stage. Each packet is an ordered array of data values, at least one of which is an instruction pointer. Each member of the ordered array can be indicative of any type of data. As a packet progresses through the pixel shader during processing, each member of the ordered array can be replaced by a sequence of data values indicative of different types of data (e. g. , an address of a texel, a texel, or a partially or fully processed color value). Information required for the pixel shader to process each packet is contained in the packet, and thus the pixel shader is scalable in the sense that it can be implemented in modular fashion to include any number of identical pipelined processing stages and can execute the same program regardless of the number of stages. Preferably, each processing stage is itself scalable, can be implemented to include an arbitrary number of identical pipelined instruction execution stages known as microblenders, and can execute the same program regardless of the number of microblenders. The current value of the instruction pointer (IP) in a packet determines the next instruction to be executed on the data contained in the packet.
Texture Cache Addressing
US Patent:
7027063, Apr 11, 2006
Filed:
May 6, 2005
Appl. No.:
11/123657
Inventors:
Alexander L. Minkin - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 17/00
US Classification:
345552, 345557, 345582, 345587, 711 3
Abstract:
A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate and at least one bit of a level of detail is discussed.
Processing High Numbers Of Independent Textures In A 3-D Graphics Pipeline
US Patent:
7245302, Jul 17, 2007
Filed:
Oct 30, 2003
Appl. No.:
10/696848
Inventors:
Christopher D. S. Donham - San Mateo CA, US
Alexander L. Minkin - Palo Alto CA, US
Alexander L. Minkin - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/14
G06T 1/00
G06T 15/60
G09G 5/00
G06T 1/00
G06T 15/60
G09G 5/00
US Classification:
345519, 345522, 345426, 345582
Abstract:
Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.
Gamma-Corrected Texel Storage In A Graphics Memory
US Patent:
7289126, Oct 30, 2007
Filed:
May 23, 2003
Appl. No.:
10/445144
Inventors:
Alexander L. Minkin - Los Altos CA, US
Harold Robert Feldman Zable - Palo Alto CA, US
Matthew N. Papakipos - Palo Alto CA, US
Harold Robert Feldman Zable - Palo Alto CA, US
Matthew N. Papakipos - Palo Alto CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/00
G06T 15/50
G06T 15/00
G06T 15/50
G06T 15/00
US Classification:
345582, 345426, 345418
Abstract:
Methods, circuits, and apparatus for handling gamma-corrected texels stored in a graphics memory. On-the-fly gamma-to-linear and linear-to-gamma conversions are performed such that gamma-corrected texels are provided to circuits that are able to process them, while linear valued texels are supplied where needed. In various embodiments, these conversions are done by lookup tables, software instructions, or dedicated hardware. Gamma-corrected texels may be tracked by a shader program, pipeline states, or driver instructions, and may be identified by header or flag information, or by part of a texture descriptor.
Processing High Numbers Of Independent Textures In A 3-D Graphics Pipeline
US Patent:
7589741, Sep 15, 2009
Filed:
Apr 17, 2007
Appl. No.:
11/736574
Inventors:
Christopher D. S. Donham - San Mateo CA, US
Alexander L. Minkin - Los Altos CA, US
Alexander L. Minkin - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/00
G06T 11/40
G06T 1/00
G06T 15/50
G06T 11/40
G06T 1/00
G06T 15/50
US Classification:
345582, 345522, 345552, 345426
Abstract:
Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.
Reconfigurable High Performance Texture Pipeline With Advanced Filtering
US Patent:
7649538, Jan 19, 2010
Filed:
Nov 3, 2006
Appl. No.:
11/556674
Inventors:
Alexander L. Minkin - Los Altos CA, US
Joel J. McCormack - Boulder CO, US
Paul S. Heckbert - Pittsburgh PA, US
Michael J. M. Toksvig - Palo Alto CA, US
Luke Y. Chang - San Mateo CA, US
Karim Abdalla - Menlo Park CA, US
Bo Hong - Fremont CA, US
John W. Berendsen - Beaconsfield, CA
Walter Donovan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Joel J. McCormack - Boulder CO, US
Paul S. Heckbert - Pittsburgh PA, US
Michael J. M. Toksvig - Palo Alto CA, US
Luke Y. Chang - San Mateo CA, US
Karim Abdalla - Menlo Park CA, US
Bo Hong - Fremont CA, US
John W. Berendsen - Beaconsfield, CA
Walter Donovan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 17/00
G06T 11/40
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/32
G06K 9/64
G06T 11/40
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/32
G06K 9/64
US Classification:
345582, 345428, 345587, 345606, 345552, 382254, 382260, 382300, 382303, 711100, 711113, 711123, 711127
Abstract:
Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
Method And Apparatus To Ensure Consistency Of Depth Values Computed In Different Sections Of A Graphics Processor
US Patent:
7659893, Feb 9, 2010
Filed:
Oct 2, 2006
Appl. No.:
11/538002
Inventors:
Stuart F. Oberman - Sunnyvale CA, US
Steven E. Molnar - Chapel Hill NC, US
Alexander L. Minkin - Los Altos CA, US
Peter B. Holmqvist - Cary NC, US
Steven E. Molnar - Chapel Hill NC, US
Alexander L. Minkin - Los Altos CA, US
Peter B. Holmqvist - Cary NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 15/40
US Classification:
345422, 345421, 345546
Abstract:
At least two different processing sections in a graphics processors compute Z coordinates for a sample location from a compressed Z representation. The processors are designed to ensure that Z coordinates computed in any unit in the processor are identical. In one embodiment, the respective arithmetic circuits included in each processing section that computes Z coordinates are “bit-identical,” meaning that, for any input planar Z representation and coordinates, the output Z coordinates produced by the circuits are identical to each other.
NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.