Chao Xu, 5610063 Parc Sky Cir, Alpharetta, GA 30022

7239188, Jul 3, 2007

Nov 1, 2005

11/264111

Chao Xu - Suwanee GA, US
Al Xuefeng Fang - Suwanee GA, US

Integrated Device Technology, Inc. - San Jose CA

H03L 7/06

327156, 327157

Clock generators include phase-locked and delay-locked loop integrated circuits that support efficient high speed testing of clock frequencies. An integrated circuit device is provided with a clock signal generator having at least one delay element therein that is responsive to a control signal. A speed tracking circuit is also provided. This speed tracking circuit is configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of the at least one delay element.

7327814, Feb 5, 2008

Jun 5, 2006

11/422252

Chao Xu - Suwanee GA, US

Integrated Device Technology, Inc. - San Jose CA

H04B 1/10

375350, 375295

A data transmitter pre-emphasizes the amplitude and frequency bandwidth of a data signal. A data tap generator delays the data signal to generate multiple data tap signals, each of which is delayed by an integer multiple of a data period. A delay module further delays one of the data tap signals by a delay time that is less than the data period to generate a delayed data signal. The delay time of the delayed data signal determines a frequency bandwidth pre-emphasis for the data signal. A filter module multiplies the amplitudes of the data tap signals and the delayed data signal by coefficients to generate signal components of a pre-emphasized data signal. The coefficients of the filter module determine the amplitude pre-emphasis for the data signal. The filter module sums the signal components to generate the pre-emphasized data signal, which includes both the frequency bandwidth pre-emphasis and the amplitude pre-emphasis.

7405594, Jul 29, 2008

Jun 16, 2006

11/424779

Chao Xu - Suwanee GA, US

Integrated Device Technology, Inc. - San Jose CA

H03K 19/0175

326 82, 326 83

A current mode driver generates a differential output signal that has a constant voltage swing between a lower voltage level and an upper voltage level. A feedback module determines an intermediate voltage between the lower voltage level and the upper voltage level, compares the intermediate voltage with a reference voltage, and generates a control signal based on a result of the comparison. The current mode driver maintains the voltage swing of the differential output signal at a constant voltage based on the control signal. The differential output signal may have a data signal component and a pre-emphasis signal component.

7545188, Jun 9, 2009

Aug 4, 2006

11/462627

Chao Xu - Suwanee GA, US
Al Xuefeng Fang - Suwanee GA, US

Integrated Device Technology, Inc - San Jose CA

H03L 7/06

327157, 327148, 327291

A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift unit selects some of the clock signals based on the control signal and generates a feedback signal based on the selected clock signals. The feedback signal has a phase based on the phases of the selected clock signals. The phase locked loop aligns the phase of the feedback signal with the phase of the input signal. In this process, the phase locked loop shifts the phase of each of the clock signals relative to the phase of the input signal.

7714620, May 11, 2010

Jun 6, 2006

11/422381

Chao Xu - Suwanee GA, US

Integrated Device Technology, Inc. - San Jose CA

H03K 5/22
H03K 5/153

327 63, 327 76, 327 75, 327 78

A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.

7750618, Jul 6, 2010

Jul 25, 2006

11/459889

Al Xuefeng Fang - Suwanee GA, US
Chao Xu - Suwanee GA, US

Integrated Device Technology, Inc. - San Jose CA

G01R 23/14

324 7641, 324 7648

A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.