Darrell Duane Boggs, 6125340 NE Bald Peak Rd, Beaverton, OR 97123

6385715, May 7, 2002

May 4, 2001

09/848423

Amit A. Merchant - Portland OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR

Intel Corporation - Santa Clara CA

G06F 1500

712219, 712 23, 712218, 709106

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e. g. , data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

6457119, Sep 24, 2002

Jul 23, 1999

09/360192

Darrell Boggs - Aloha OR
Robert F. Krick - Fort Collins CO
Chan Lee - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

712227, 712231

Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

6467027, Oct 15, 2002

Dec 30, 1999

09/475746

Alan B. Kyker - Portland OR
Darrell D. Boggs - Aloha OR

Intel Corporation - Santa Clara CA

G06F 1200

711125, 711141

A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

6496925, Dec 17, 2002

Dec 9, 1999

09/458544

Dion Rodgers - Hillsboro OR
Darrell Boggs - Aloha OR
Amit Merchant - Portland OR
Rajesh Kota - Aloha OR
Rachel Hsu - Hillsboro OR
Keshavan Tiruvallur - Tigard OR

Intel Corporation - Santa Clara CA

G06F 938

712244, 712216, 712218, 712 1, 710262

A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this second thread. Responsive to the detection of a clearing point for the second thread, a functional unit within the multithreaded processor is cleared of data for both the first and the second threads.

6591344, Jul 8, 2003

Aug 15, 2002

10/218628

Alan B. Kyker - Portland OR
Darrell D. Boggs - Aloha OR

Intel Corporation - Santa Clara CA

G06F 1200

711125, 711117, 711123, 711202, 711206, 711205, 712205, 712226

A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

6633970, Oct 14, 2003

Dec 28, 1999

09/472840

David W. Clift - Hillsboro OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

712217, 712 23, 712218

A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e. g. , from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path. The secondary array is movable to a particular speculative state based on the mappings stored in the history buffer, such as to a location where a path failure may occur. The secondary array can then be copied to the primary array when a failure is detected in a predicted path of instructions near where the secondary array is located to allow the processor to recover from the predicted path failure.

6651158, Nov 18, 2003

Jun 22, 2001

09/888274

David W. Burns - Portland OR
James D. Allen - Portland OR
Michael D. Upton - Portland OR
Darrell D. Boggs - Aloha OR
Alan B. Kyker - Davis CA

Intel Corporation - Santa Clara CA

G06F 946

712205, 709103

In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

6665792, Dec 16, 2003

Dec 30, 1999

09/475029

Amit A. Merchant - Portland OR
Darrell D. Boggs - Aloha OR
David J. Sager - Portland OR

Intel Corporation - Santa Clara CA

G06F 900

712219, 712 32, 712225

A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.