David S Mui, 6448472 Arkansas Pl, Fremont, CA 94539

6458671, Oct 1, 2002

Feb 16, 2001

09/784997

Wei Liu - Sunnyvale CA
David Mui - San Jose CA

Applied Materials Inc. - Santa Clara CA

H01L 2120

438391, 438248, 438424, 438734

A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1 and (b) a second plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably 1. 3:1:1.

6566270, May 20, 2003

Sep 15, 2000

09/662677

Wei Liu - San Jose CA
Scott Williams - Sunnyvale CA
Stephen Yuen - Santa Clara CA
David Mui - San Jose CA
Meihua Shen - Fremont CA

Applied Materials Inc. - Santa Clara CA

H01L 21302

438706, 438714, 438719, 134 11, 134 12

A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

6589715, Jul 8, 2003

Mar 15, 2001

09/810369

Olivier Joubert - Meylan, FR
Cedric Monget - Grenoble, FR
Timothy Weidman - Sunnyvale CA
Dian Sugiarto - Union City CA
David Mui - San Jose CA

France Telecom - Meylan Cedex
Applied Materials, Inc. - Santa Clara CA

G03F 736

430316, 430311, 430313, 430322, 430323, 430329, 216 67, 216 72, 438714, 438734, 438735, 427488, 427489

A process for etching a PPMS layer that increases the etch selectivity of PPMS relative to PPMSO from an initial low etch selectivity to a higher etch selectivity at a later stage of the etching process. In some embodiments, the etch selectivity used during a first etching step of the process is less than 4:1 and the etch selectivity used during a second etching step, subsequent to the first step, is greater than 5:1. In some other embodiments, the etch selectivity of the first step is between 2-3:1 and the etch selectivity of the second step is greater than 8:1. Optionally, in still other embodiments a third etching step, performed between the first and second etching steps may be employed where the etch selectivity is between 3-8:1.

6589879, Jul 8, 2003

Jan 18, 2001

09/766187

Scott M. Williams - Sunnyvale CA
Wei Liu - Sunnyvale CA
David Mui - San Jose CA

Applied Materials, Inc. - Santa Clara CA

H01L 21302

438714, 438719, 438723, 438724

A nitride etch process particularly useful when integrated with a silicon trench etch needing a sloping silicon surface adjacent to the interface between the silicon and an oxide layer intermediate the silicon and nitride. The nitride etch process is a plasma process having an etching gas mixture of sulfur hexafluoride (SF ) and trifluoromethane (CHF ) although nitrogen or oxygen may be added for additional controls. The trifluoromethane is believed to create a polymer passivation on the sidewalls of the hole being etched which, when the etch reaches the oxide-silicon interface, protects the interface and underlying silicon. The nitride etch may proceed through the oxide or a separate fluorocarbon-based oxide etching step may be performed before a bromine-based etch of the silicon starts.

6632321, Oct 14, 2003

Jan 5, 1999

09/225825

Thorsten Lill - Sunnyvale CA
David Mui - Santa Clara CA
Michael Grimbergen - Redwood City CA

Applied Materials, Inc - Santa Clara CA

C23F 100

15634524, 15634526, 15634527, 15634528

A method and apparatus for monitoring, measuring and/or controlling the etch rate in a dry etch semiconductor wafer processing system. The wafer processing system has a monitoring assembly which comprises an electromagnetic radiation source and detector which interferometrically measures the etch rate. The actual rate of change of the etch as it progresses is measures by this technique and is compared to a model of a desired rate of change in a controller. The error between the actual rate of change and the desired rate of change is then used to vary at least one of the process parameters of the system in a direction tending to null the difference.

6653237, Nov 25, 2003

Jun 27, 2001

09/893859

Shashank Deshmukh - San Jose CA
David Mui - San Jose CA
Jeffrey D. Chinn - Foster City CA
Dragan V Podlesnik - Palo Alto CA

Applied Materials, Inc. - Santa Clara CA

H01L 21302

438700, 438706, 438712, 438719

Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF , at least one fluorocarbon gas, and N. If desired, Cl can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

6677242, Jan 13, 2004

Aug 12, 2000

09/637838

Wei Liu - San Jose CA
Scott Williams - Sunnyvale CA
Stephen Yuen - Santa Clara CA
David Mui - San Jose CA

Applied Materials Inc. - Santa Clara CA

H01L 21302

438706, 438714, 438719, 134 11, 134 12

A method for processing a silicon substrate disposed in a substrate process chamber includes transferring the substrate into the substrate process chamber. The substrate having a hard mask formed thereon and a patterned photoresist overlying the hard mask to expose portions of the hard mask. The chamber being the type having a source power system and a bias power system. The method further includes etching the exposed portions of the hard mask to expose portions of the silicon substrate underlying the hard mask. Thereafter, the patterned photoresist is exposed to a first plasma formed from a first process gas to remove the photoresist from the hard mask. Thereafter, the exposed silicon substrate is etched by exposing the substrate to a second plasma formed from a second process gas by applying RF energy from the source power system and biasing the plasma toward the substrate. The substrate is transferred out of the substrate processing chamber.

6703315, Mar 9, 2004

Jun 10, 2002

10/165894

Wei Liu - Sunnyvale CA
David Mui - San Jose CA

Applied Materials Inc. - Santa Clara CA

H01L 21302

438706, 438712, 438720, 438723

A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1 and (b) a second plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably 1. 3:1:1.