Dongjiang Qiao, 5311409 Trailbrook Ln, San Diego, CA 92128

7904045, Mar 8, 2011

Jun 29, 2007

11/771267

Ichiro Aoki - San Clemente CA,
Scott D. Kee - Dana Point CA,
Dongjiang Qiao - San Diego CA,
Alyosha C. Molnar - Berkeley CA,

Axiom Microdevices, Inc. - Woburn MA

H04B 1/06

455260, 455 76, 4551651, 455255, 455261, 455265, 455 75, 455258, 455318, 4551803, 455147, 375355, 375239, 375371, 375373, 375295, 375316, 375300, 375259, 327291, 327161, 327162, 327156, 360 32, 370485, 331 11

A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

8265568, Sep 11, 2012

Mar 19, 2009

12/407700

Dongjiang Qiao - San Diego CA,
Frederic Bossu - San Diego CA,

Qualcomm Incorporated - San Diego CA

H03K 25/00

455 76, 327115, 327117

A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

8344765, Jan 1, 2013

Jul 14, 2010

12/836454

Dongjiang Qiao - San Diego CA,
Frederic Bossu - San Diego CA,

QUALCOMM, Incorporated - San Diego CA

H03B 19/06
H03K 21/00

327118, 327115, 327117, 377 47

A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

8368434, Feb 5, 2013

Jul 15, 2010

12/836774

Aleksandar M. Tasic - San Diego CA,
Junxiong Deng - San Diego CA,
Dongjiang Qiao - San Diego CA,

Qualcomm Incorporated - San Diego CA

H03K 21/00

327115, 327117, 377 47

A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

8570076, Oct 29, 2013

Jul 1, 2010

12/829107

Gary L. Brown - San Diego CA,
Alberto Cicalini - San Diego CA,
Dongjiang Qiao - San Diego CA,

Qualcomm Incorporated - San Diego CA

H03B 19/06

327118, 327117

A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

2010003, Feb 18, 2010

Aug 18, 2008

12/193693

Dongjiang Qiao - San Diego CA,
Frederic Bossu - San Diego CA,

QUALCOMM Incorporated - San Diego CA

H03H 11/16

327254

A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

2011001, Jan 20, 2011

Mar 15, 2010

12/724337

Dongjiang Qiao - San Diego CA,
Bhushan S. Asuri - San Diego CA,
Junxiong Deng - San Diego CA,
Frederic Bossu - San Diego CA,

QUALCOMM INCORPORATED - San Diego CA

H03L 7/00

327141

A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.