Gerhard Muller, 81Garden City, NY

2002011, Aug 22, 2002

Nov 2, 2001

10/001176

Gerhard Muller - Hopewell Jct NY, US

G11C008/00

365/230030

The data memory has a plurality of banks, each with a multiplicity of memory cells that form a matrix of rows and columns with respectively assigned matrix row lines and column lines. The banks are arranged spatially one on top of the other as stacks, with the stack edges that are parallel to the matrix rows and at which the ends of the column lines that are connected to a respective column-driving device are located, lie in a common plane. The common plane extends in the direction of the matrix rows and is substantially orthogonal with respect to the direction of the columns. The column-driving devices of all the banks are arranged directly adjacent to one another as a block in the direction of the columns, on or near the same edge of the bank stack. The banks preferably contain memory cells which can be read out without damage, and in each case a plurality of column lines are each assigned to one common sense amplifier in the column-driving device of each bank.

5966315, Oct 12, 1999

Sep 30, 1997

8/942275

Gerhard Muller - Wappingers Falls NY
Heinz Hoenigschmid - Starngberg, DE

Siemens Aktiengesellschaft - Munich

G11C 502
G11C 506
G11C 702

365 51

Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL. sub. 1, LBL. sub. 2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SA. sub. i). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i. e. , the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL. sub. 1) in a column is directly coupled via a switch (25. sub. 1) to an associated sense amplifier, whereas the other local bit lines in the column (LBL. sub. 2 -LBL. sub. 4) are operatively coupled to the sense amplifier via the master bit line. The different local bit line lengths are preferably selected such that total bit line capacitance with respect to any of the memory cells is substantially equalized, thereby improving data retention time for the memory.

6069491, May 30, 2000

Oct 19, 1998

9/174745

Gerhard Muller - Wappingers Falls NY
Thomas Kristoffersson - Munchen, DE

Siemens Aktiengesellschaft - Munich

H03K 190185

326 70

The buffer circuit of the invention converts TTL level input signals to CMOS level output signals. The buffer circuit has three inverter stages, in which the output signal of one stage is positively fed back, in order to achieve complete modulation. Because of a current limiting circuit, the current consumption of the buffer circuit does not exceed a defined value. Despite a high switching speed, the power consumption of the circuit is low.