James D Chlipala, 784754 White Oak Cir, Emmaus, PA 18049

6700944, Mar 2, 2004

May 30, 2000

09/583115

James D. Chlipala - Emmaus PA
John M. Khoury - Basking Ridge NJ
Kadaba R. Lakshmikumar - Basking Ridge NJ
Peter C. Metz - Macungie PA

Agere Systems Inc. - Allentown PA

H03D 324

375376, 375375, 327156

A method and apparatus for detecting the phase difference between an input data signal and a local clock signal is provided. An input data signal is frequency divided and then fed through a series connection of a pair of data latches. Signals provided at the input and outputs of the pair of the data latches are exclusively-ORed to provide a variable width pulse signal and a reference pulse signal that may be used in a phase-locked loop to align the local clock with the input data signal in a predetermined phase relationship. A re-timed data signal is provided by inputting the input data signal to a data latch clocked with an inverted phase-aligned clock signal.

7218557, May 15, 2007

Dec 23, 2005

11/318952

James D. Chlipala - Emmaus PA, US
Mohammad S. Mobin - Orefield PA, US

Agere Systems Inc. - Allentown PA

G11C 8/18

365193, 36518907, 365233

Methods and apparatus are provided for adaptive determination of timing signals, such as on a high speed parallel bus. The invention adaptively determines a timing signal having a first edge with respect to an internal clock, wherein the timing signal includes a period in which the timing signal is undriven, followed by a period immediately before a first transition in which the timing signal is in a predefined state. The timing signal is evaluated using one or more comparators; and an output of the one or more comparators are latched based on a clock signal. The clock signal is adjusted until the one or more comparators indicate the timing signal is in the known and valid state. The clock signal is further adjusted until the one or more comparators indicate the first transition has been reached. Thereafter, a gating control signal is established based on a timing of the first transition.

7366086, Apr 29, 2008

Feb 18, 2004

10/780945

Christopher J. Abel - Coplay PA, US
Joseph Anidjar - Asbury NJ, US
James D. Chlipala - Emmaus PA, US
Abhishek Duggal - Allentown PA, US
Donald R. Laturell - Allentown PA, US

Agere Systems Inc. - Allentown PA

H04J 1/12

370201, 370508

A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

7786814, Aug 31, 2010

Aug 28, 2008

12/199881

Michael S. Buonpane - Easton PA, US
James D. Chlipala - Emmaus PA, US
Richard P. Martin - Macungie PA, US
Scott A. Segan - Allentown PA, US
Zhongke Wang - Bridgewater NJ, US

Agere Systems Inc. - Allentown PA

H03B 5/24

331 57, 331 44

Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.

8161431, Apr 17, 2012

Oct 30, 2008

12/261738

Michael S. Buonpane - Easton PA, US
James D. Chlipala - Emmaus PA, US
Richard P. Martin - Macungie PA, US
Richard Muscavage - Gilbertsville PA, US
Scott A. Segan - Allentown PA, US

Agere Systems Inc. - Allentown PA

G06F 17/50
G06F 11/22
G06F 11/00
G06F 1/26
G01K 1/08

716100, 716101, 716136, 716138, 374141, 714 10, 714 22, 713320

Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

8180600, May 15, 2012

Aug 31, 2006

11/469028

James D. Chlipala - Emmaus PA, US
Makeshwar Kothandaraman - Whitehall PA, US
Nirav Patel - Bangalore, IN
Venu Babu Ummalaneni - Guntur, IN

Agere Systems Inc. - Allentown PA

G06F 7/60
G06F 17/50

703 2, 716101

In one embodiment, the invention is a method for modeling electrical behavior of a packaged module having multiple integrated circuits (ICs), such as a multi-chip module (MCM). The method includes: (a) identifying one or more pin groups in the module, wherein a pin group comprises two or more buffers connected together and to a package-external pin, and (b) generating one or more corresponding unified behavioral models for the one or more pin groups based on the characteristics of the buffers of the one or more pin groups. The behavioral models are part of an integrated behavioral model file in accordance with the I/O buffer information specification (IBIS) standard.

8350589, Jan 8, 2013

Jan 27, 2009

12/738931

James D. Chlipala - Emmaus PA, US
Richard P. Martin - Macungie PA, US
Richard Muscavage - Gilbertsville PA, US
Scott A. Segan - Allentown PA, US

Agere Systems LLC - Wilmington DE

H03K 19/00
G01R 31/28

326 16, 714724

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

2008012, Jun 5, 2008

Nov 30, 2006

11/565067

James D. Chlipala - Emmaus PA, US
Scott A. Segan - Allentown PA, US

H03L 7/00

327161

Apparatus for correcting clock skew in a circuit including at least one sequential circuit element and a clock generator operatively coupled to the sequential circuit element includes at least one programmable delay element connected in series with a data input and/or a clock input of the sequential circuit element. The programmable delay element has a delay associated therewith which is selectively controllable as a function of a control signal. The apparatus further includes at least one processor connected in a feedback configuration with the sequential circuit element. The processor is operative to receive a clock signal generated by the clock generator and an output signal of the sequential circuit element and to generate the control signal as a function of the clock signal and the output signal. The processor is further operative to control a timing of a data signal supplied to the data input of the sequential circuit element.