Search For

Jonathan W Babb, 49Watertown, MA

Jonathan Babb Phones & Addresses

Watertown, MA   

975 Memorial Dr, Cambridge, MA 02138    617-6611132   

47 University Pl, Princeton, NJ 08540    609-6834923   

Charlestown, MA   

Boston, MA   

20 Watertown St UNIT 205, Watertown, MA 02472   

Social networks

Jonathan W Babb

Linkedin

Work

Company: Operation simulation associates Position: Consultant

Education

Degree: PHD School / High School: Massachusetts Institute of Technology 1994 to 2001 Specialities: Electrical Engineering and Computer Science

Industries

Renewables & Environment

Mentions for Jonathan W Babb

Resumes

Resumes

Jonathan Babb Photo 1

Consultant At Operation Simulation Associates

Position:
Consultant at Operation Simulation Associates
Location:
Greater Boston Area
Industry:
Renewables & Environment
Work:
Operation Simulation Associates
Consultant
Education:
Massachusetts Institute of Technology 1994 - 2001
PHD, Electrical Engineering and Computer Science
Massachusetts Institute of Technology 1991 - 1994
MS, Electrical Engineering and Computer Science
Georgia Institute of Technology 1987 - 1991
BS, Electrical Engineering

Publications

Us Patents

Bio-Field Programmable Gate Array And Bio-Programmable Logic Array: Reconfigurable Chassis Construction

US Patent:
2011025, Oct 20, 2011
Filed:
Nov 15, 2010
Appl. No.:
12/946604
Inventors:
Jonathan William Babb - Watertown MA,
Ron Weiss - Newton MA,
Thomas Knight - Cambridge MA,
Adam Rubin - Cleveland OH,
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
C40B 40/08
C12N 15/64
C12N 1/21
US Classification:
506 17, 4352523, 43525233, 435 914
Abstract:
Aspects of the invention relate to reconfigurable chassis that allow for rapid construction and optimization of biocircuits.

Programmable Multiplexing Input/output Port

US Patent:
5847578, Dec 8, 1998
Filed:
Jan 8, 1997
Appl. No.:
8/780527
Inventors:
Michael Donald Noakes - Somerville MA
Charles W. Selvidge - Charlestown MA
Anant Argarwal - Framingham MA
Jonathan Babb - Ringgold GA
Matthew L. Dahl - Marlborough MA
Assignee:
Virtual Machine Works - Cambridge MA
International Classification:
H03K 738
H03K 1900
US Classification:
326 39
Abstract:
A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.

Virtual Interconnections For Reconfigurable Logic Systems

US Patent:
5761484, Jun 2, 1998
Filed:
Sep 28, 1995
Appl. No.:
8/530323
Inventors:
Anant Agarwal - Framingham MA
Jonathan Babb - Cambridge MA
Russell Tessier - Cambridge MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
G06F 1750
US Classification:
395500
Abstract:
A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.

Virtual Interconnections For Reconfigurable Logic Systems

US Patent:
5596742, Jan 21, 1997
Filed:
Apr 2, 1993
Appl. No.:
8/042151
Inventors:
Anant Agarwal - Framingham MA
Jonathan Babb - Ringgold GA
Russell Tessier - Cambridge MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
G06F 1750
US Classification:
395500
Abstract:
A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.

All data offered is derived from public sources. We do not verify or evaluate each piece of data, and makes no warranties or guarantees about any of the information offered. We do not possess or have access to secure or private financial information. Background Check is not a credit reporting agency and does not offer consumer reports. None of the information offered by Background Check is to be considered for purposes of determining any entity or person's eligibility for credit, insurance, employment, housing, or for any other purposes covered under the FCRA.