Jonathan W Babb, ~52Lexington, MA

2011025, Oct 20, 2011

Nov 15, 2010

12/946604

Jonathan William Babb - Watertown MA,
Ron Weiss - Newton MA,
Thomas Knight - Cambridge MA,
Adam Rubin - Cleveland OH,

Massachusetts Institute of Technology - Cambridge MA

C40B 40/08
C12N 15/64
C12N 1/21

506 17, 4352523, 43525233, 435 914

Aspects of the invention relate to reconfigurable chassis that allow for rapid construction and optimization of biocircuits.

5847578, Dec 8, 1998

Jan 8, 1997

8/780527

Michael Donald Noakes - Somerville MA
Charles W. Selvidge - Charlestown MA
Anant Argarwal - Framingham MA
Jonathan Babb - Ringgold GA
Matthew L. Dahl - Marlborough MA

Virtual Machine Works - Cambridge MA

H03K 738
H03K 1900

326 39

A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.

5761484, Jun 2, 1998

Sep 28, 1995

8/530323

Anant Agarwal - Framingham MA
Jonathan Babb - Cambridge MA
Russell Tessier - Cambridge MA

Massachusetts Institute of Technology - Cambridge MA

G06F 1750

395500

A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.

5596742, Jan 21, 1997

Apr 2, 1993

8/042151

Anant Agarwal - Framingham MA
Jonathan Babb - Ringgold GA
Russell Tessier - Cambridge MA

Massachusetts Institute of Technology - Cambridge MA

G06F 1750

395500

A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.