Michael J Cadigan, 67Leander, TX
Michael Cadigan Phones & Addresses
Leander, TX
Buffalo, NY
Poughkeepsie, NY
Hamburg, NY
Brewster, NY
Westland, MI
Lake View, NY
Erin, NY
Austin, TX
Mentions for Michael J Cadigan
Publications & IP owners
Us Patents
Chip Having Timing Analysis Of Paths Performed Within The Chip During The Design Process
US Patent:
2008005, Feb 28, 2008
Filed:
Oct 22, 2007
Appl. No.:
11/876400
Inventors:
James Curtin - Fishkill NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin Mcllvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin Mcllvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716006000
Abstract:
An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
Chip Having Timing Analysis Of Paths Performed Within The Chip During The Design Process
US Patent:
2008006, Mar 13, 2008
Filed:
Nov 5, 2007
Appl. No.:
11/934995
Inventors:
James Curtin - Fishkill NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin McIlvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin McIlvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716006000
Abstract:
An integrated Circlet chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
Genie: A Method For Classification And Graphical Display Of Negative Slack Timing Test Failures
US Patent:
2006001, Jan 12, 2006
Filed:
May 16, 2005
Appl. No.:
11/129784
Inventors:
James Curtin - Fishkill NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin McIlvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin McIlvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
International Classification:
G06F 17/50
G06F 9/45
G06F 9/45
US Classification:
716006000, 716010000
Abstract:
Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.
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