Nobuyuki Suzuki7623 NW 170Th Ave, Portland, OR 97229

2021011, Apr 22, 2021

Dec 26, 2020

17/134293

- Santa Clara CA, US
Nobuyuki Suzuki - Portland OR, US
Anoop Mukker - Folsom CA, US
Daniel Nemiroff - El Dorado Hills CA, US
David W. Vogel - Sacramento CA, US

G06F 13/42
G06F 1/08
G06F 1/24
G06F 1/3287
G06F 9/4401

An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

2020035, Nov 12, 2020

Jan 22, 2019

16/254266

- Santa Clara CA, US
Nobuyuki Suzuki - Portland OR, US
Anoop Mukker - Folsom CA, US
Daniel Nemiroff - El Dorado Hills CA, US
David W. Vogel - Sacramento CA, US

G06F 13/42
G06F 1/08
G06F 1/24
G06F 1/3287
G06F 9/4401

An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

2019004, Feb 7, 2019

Feb 26, 2018

15/905562

- Santa Clara CA, US
Karthi Vadivelu - Folsom CA, US
Abdul Ismail - Beaverton OR, US
Antonio Cheng - Portland OR, US
Nobuyuki Suzuki - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 13/42
G06F 13/36
G06F 13/40

A Universal Serial Bus (USB) circuitry of an apparatus is disclosed. In an example, the USB circuitry includes a High Speed (HS) transmitter to transmit data at a first data rate from the apparatus to a component; and a pair of Low Speed/Full speed (LS/FS) receivers to receive data at one or both of a second data rate or a third data rate from the component. In an example, the USB circuitry is to refrain from receiving data from the component at the first data rate.

2019004, Feb 7, 2019

Dec 29, 2017

15/858678

- Santa Clara CA, US
Nausheen Ansari - Folsom CA, US
Nobuyuki Suzuki - Portland OR, US
Zhiming Zhuang - Sammamish WA, US
Atsuo Kuwahara - Portland OR, US
Gary K. Smith - El Dorado Hills CA, US

G06T 3/40
G06T 11/60
G06T 1/60
G06T 1/20

Example methods, apparatus, systems and articles of manufacture (e.g., non-transitory physical storage media) to implement foveated image rendering for head-mounted displays device are disclosed herein. Example head-mounted display devices disclosed herein include a frame buffer to store first and second image data for an image frame, the first image data having a first resolution and the second image data having a second resolution lower than the first resolution, the first image data and the second image data obtained from a host device via a data interface. Disclosed example head-mounted display devices also include a device controller to up-sample the second image data based on first metadata from the host device to generate up-sampled second image data having the first resolution, and combine the first image data and the up-sampled second image data based on second metadata from the host device to render a foveated image frame on a display.

2019004, Feb 7, 2019

Sep 27, 2018

16/144346

- Santa Clara CA, US
Nausheen Ansari - Folsom CA, US
Nobuyuki Suzuki - Portland OR, US
Zhiming Zhuang - Sammamish WA, US

G09G 5/12
G06F 1/16
G06F 3/14
G09G 5/18

Methods and apparatus for synchronizing embedded display panels of mobile devices via programmable synchronization links are disclosed. An example mobile device includes a first embedded display panel, a second embedded display panel, a programmable synchronization link, a configuration manager, and a synchronization manager. The programmable synchronization link is operatively coupled to the first and second embedded display panels. The configuration manager is to configure the first embedded display panel as a slave panel, and to configure the second embedded display panel as a master panel. The synchronization manager is to synchronize the slave panel to the master panel via the programmable synchronization link.

2019004, Feb 7, 2019

Apr 3, 2018

15/944344

- Santa Clara CA, US
Nobuyuki Suzuki - Portland OR, US
Zhiming Zhuang - Sammamish WA, US

Intel Corporation - Santa Clara CA

H04N 5/04

Technology for a display device is described. The display device can include one or more display screens operable to show at least two display panels. The display device can include a controller. The controller can send a request for frame data from each of the at least two display panels to a source device. The controller can receive, from the source device, a same frame indication for each of the at least two display panels. The controller can provide frame data received from the source device based on the same frame indication to the at least two display panels. The same frame indication can cause the at least two display panels to synchronously display frame data received from the source device.

2019000, Jan 3, 2019

Jun 28, 2017

15/635299

Kenneth P. Foust - Beaverton OR, US
Amit Kumar Srivastava - Penang, MY
Nobuyuki Suzuki - Portland OR, US

G06F 13/42
G06F 13/364
G06F 13/24

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

2018037, Dec 27, 2018

Jun 22, 2017

15/630477

- Santa Clara CA, US
Aaron J. Steyskal - Portland OR, US
Nobuyuki Suzuki - Portland OR, US

Intel Corporation - Santa Clara CA

G02F 1/1335
G09G 5/02
G02F 1/1347
G09G 3/36
H04N 5/57
H04N 9/12
H04N 9/31

Methods of forming display structures, and structures formed thereby are described. Display structures formed may include a display device comprising an emissive layer that includes an array of pixels, wherein each of the individual pixels of the pixel array are capable of emitting light in at least two directions. A controllable opacity layer may be disposed on the emissive layer, wherein the controllable opacity layer is capable of at least partially blocking light emission from the array of pixels.