Paul K Cheung, 75Chelsea, MA

6774694, Aug 10, 2004

Dec 24, 2002

10/328637

Kenneth J. Stern - Watertown MA
Jeff W. Barrell - Newton MA
Paul S. Cheung - North Andover MA
Thomas Alan Gaiser - Amherst NH

Analog Devices, Inc. - Norwood MA

H03H 1126

327276, 327284, 327294

A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

2012029, Nov 22, 2012

May 18, 2011

13/110284

Javier A. Salcedo - North Billerica MA, US
Paul Cheung - North Andover MA, US

Analog Devices, Inc. - Norwood MA

H02H 3/22

361111

Apparatus and methods for integrated circuit protection are provided. In one embodiment, an integrated circuit (IC) includes a first pad, a second pad, a third pad, a first protection subcircuit coupled between the first pad and a common node, a second protection subcircuit coupled between the second pad and the common node, and a third protection subcircuit coupled between the third pad and the common node. The first, second, and third protection subcircuits each include one or more building blocks for maintaining the voltage of each of the pads within a predefined safe range, as well as to maintain the voltage between each of the pads within acceptable limits. A portion of the building blocks used to provide transient signal protection can be shared between pads, thereby reducing the area of the pad protection circuit relative to a scheme using a separate stack of building blocks for each pad.