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Robert L Wadsworth, ~65Sahuarita, AZ

Robert Wadsworth Phones & Addresses

Sahuarita, AZ   

7909 Freeland Dr, Plano, TX 75025    972-3988838   

Pima, AZ   

Tucson, AZ   

7909 Freeland Dr, Plano, TX 75025   

Work

Company: Animal inn Address: 6745 N La Canada Dr, Tucson, AZ 85704 Position: Partner Industries: Animal Specialty Services, Except Veterinary

Education

Degree: Associate degree or higher

Mentions for Robert L Wadsworth

Resumes

Resumes

Robert Wadsworth Photo 1

Principal Engineer At St Microelectronics

Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Robert Wadsworth Photo 2

Robert Wadsworth

Location:
United States
Robert Wadsworth Photo 3

Robert Wadsworth

Location:
United States
Robert Wadsworth Photo 4

Robert Wadsworth

Location:
United States

Business Records

Name / TitleCompany / ClassificationPhones & Addresses
Robert Wadsworth
Partner
Animal Inn
Animal Specialty Services, Except Veterinary
6745 N La Canada Dr, Tucson, AZ 85704
Robert Wadsworth TAP PROPERTIES, LLC
Robert Wadsworth PORT CONNEAUT PROPERTIES, LLC
Robert Wadsworth SALMON INVESTMENTS LTD

Publications

Us Patents

Structure And Method With Which To Generate Data Background Patterns For Testing Random-Access-Memories

US Patent:
6477673, Nov 5, 2002
Filed:
Jul 30, 1999
Appl. No.:
09/365125
Inventors:
Richard J. Ferrant - St. Ismier,
Robert Alan Wadsworth - Coppell TX
Assignee:
STMicroelectronics, Inc. - Carrollton TX
International Classification:
H04B 1700
US Classification:
714728, 714724
Abstract:
Programmability of the data background patterns used to test random-access-memories (RAMs) is accomplished by adding to the memory input/output (I/O) buffers of RAM memory, for each data bit of a data background pattern to be programmed, a programming mechanism and a selection mechanism. The programming mechanism is capable of programming a data bit of the data background pattern in accordance with a programming information signal provided to the RAM. The selection mechanism provides either the programmed data bit or a normal, application data bit to an input/output buffer of the RAM in accordance with whether the RAM is in a test mode or a normal operating mode, as indicated by a test control signal provided to the RAM.

Test Mode Circuitry For A Programmable Tamper Detection Circuit

US Patent:
7978095, Jul 12, 2011
Filed:
Jun 23, 2006
Appl. No.:
11/473451
Inventors:
David C. McClure - Carrollton TX,
Sooping Saw - The Colony TX,
Robert Wadsworth - Flower Mound TX,
Assignee:
STMicroelectronics, Inc. - Coppell TX
International Classification:
G08B 13/14
US Classification:
34087002, 34087001, 34087009, 340 101, 340 102, 340 103, 340 104, 340 105, 340 106, 34053931, 340590, 340506, 340507, 36518912, 36518902, 36523102
Abstract:
An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode.

Test Mode Circuitry For A Programmable Tamper Detection Circuit

US Patent:
2011014, Jun 23, 2011
Filed:
Mar 3, 2011
Appl. No.:
13/039832
Inventors:
David C. McClure - Carrollton TX,
Sooping Saw - The Colony TX,
Robert Wadsworth - Flower Mound TX,
Assignee:
STMICROELECTRONICS, INC. - Coppell TX
International Classification:
G08B 29/00
US Classification:
340514
Abstract:
An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

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