Rory L Fisher, 586038 Huntington Hills Dr, Fort Collins, CO 80525

6539507, Mar 25, 2003

Nov 10, 1999

09/437813

Christopher M Juenemann - Aurora CO
Bradley J Goertzen - Ft. Collins CO
Rory L Fisher - Fort Collins CO
Randy L Fiscus - Ft. Collins CO
Brian C Miller - Fort Collins CO
Peter J Meier - Fort Collins CO
Joel Buck-Gengler - Longmont CO
Kenneth S Bower - Ft. Collins CO
Michael R Diehl - Fort Collins CO
Dale R Beucler - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G01R 3128

714726

An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

6721923, Apr 13, 2004

Feb 20, 2002

10/079337

Rory L. Fisher - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G06F 1750

716 1, 716 3, 716 4, 716 5, 716 18

A system and method for generating a boundary-scan description language file is disclosed. In a simplified embodiment of the invention, the system utilizes a memory; software stored within the memory defining functions to be performed by the system; and a processor. The processor is configured by the software to: create a flat netlist that describes the integrated circuit, wherein the flat netlist comprises connectivity information regarding leaf cells within the integrated circuit; determine and store a name provided for each joint test action group register located within the integrated circuit, from the created flat netlist; determine relationships between each joint test action group register located within the integrated circuit and at least one input/output pin located within the integrated circuit, from the created flat netlist, and store a description of the relationships; and create a boundary-scan description language file from the stored names of each joint test action group and the stored description of the relationship between the joint test action group register and the input/output pin.

2003022, Nov 27, 2003

May 24, 2002

10/155549

Rory Fisher - Fort Collins CO, US

G06F017/50

716/005000, 716/004000, 716/012000

A method and apparatus provided for analyzing connectivity conditions in a netlist data file. The hierarchy of the netlist data file is traversed and nets and leaf cells are identified. Connections between nets and leaf cells are identified. Once the connections between nets and leaf cells have been identified, determinations are made as to whether the leaf cells are properly connected to their respective nets. Conditions such as gate-only nets, zero-connects, one-connects, drive fights, floating-nets and port-direction mismatches are identified by analyzing the connections between nets and leaf cells. Determinations may then be made as to whether a condition has been detected that should be corrected.

2004009, May 20, 2004

Nov 20, 2002

10/300513

Rory Fisher - Fort Collins CO, US

G01R031/28

714/726000

An automated test method and apparatus are presented for checking the integrity of a scan chain. The automated test method implements a process that identifies specific configuration problems that are not discovered with conventional test procedures. The automated test method accesses a circuit such as an integrated circuit, which is represented as a network list of elements. The automated test method traverses the network list of elements in a forward direction and in a backward direction to identify configuration problems such as () a scan chain with multiple drivers; () multiple test signals associated with a scan chain () a broken scan chain; () a gated signal problem, and () a loop-back condition.

2008024, Oct 2, 2008

Mar 28, 2007

11/692601

Rory L. Fisher - Fort Collins CO, US

G06F 11/00

714741

A method, system and program reduce ATPG processing times by eliminating non-value added cells in a circuit model that that is provided to an ATPG system. The elimination of non-value added cells results in a logically equivalent circuit model that is reduced in size from an original circuit model. As a result, an ATPG system that receives the modified circuit model generates a set of test vectors in a shorter amount of time. The method, system and program identify select cells in accordance with information provided in an original circuit model that defines each of the separate circuit cells. Leaf cells, a specific type of cell, are processed using a first set of conditions to generate a modified cell definition. Thereafter, a second set of conditions are applied to generate a modified circuit model.