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Steve C Yeung, 89San Jose, CA

Steve Yeung Phones & Addresses

San Jose, CA   

8400 Oceanview Ter, San Francisco, CA 94132    650-7563984    650-7571630   

8400 Oceanview Ter APT 219, San Francisco, CA 94132    650-7571269   

108 Lapham Way, San Francisco, CA 94112    415-4697760   

Daly City, CA   

Mentions for Steve C Yeung

Resumes & CV records

Resumes

Steve Yeung Photo 35

Research & Development In Santur Corporation

Location:
San Francisco Bay Area
Industry:
Telecommunications
Steve Yeung Photo 36

Product Manager At E*Trade Financial

Location:
San Francisco Bay Area
Industry:
Financial Services
Steve Yeung Photo 37

Software Engineer

Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Netapp
Software Engineer
Cisco Jun 2000 - Aug 2005
Software Engineer Iv
Efi Dec 1995 - Jun 2000
Lead Software Engineer
Embedded Performance Jun 1991 - Dec 1995
Senior Software Engineer
Education:
University of Wisconsin - Madison
Bachelors, Bachelor of Science
Skills:
Device Drivers, Unix, Linux, Embedded Software, Debugging, Software Development, Vxworks, Switches, Firmware, Linux Kernel, Voip, Software Design, Testing, Tcp/Ip, Embedded Systems, Distributed Systems
Steve Yeung Photo 38

Steve Yeung

Steve Yeung Photo 39

Steve Yeung

Steve Yeung Photo 40

Steve Yeung

Steve Yeung Photo 41

System Design Engineer At Optisolar Technologies Inc.

Location:
San Francisco Bay Area
Industry:
Utilities
Steve Yeung Photo 42

Steve Yeung

Location:
United States

Publications & IP owners

Us Patents

Gsm Transceiver With Time Division Duplexed Operations For Receiving Data, Monitoring Signal Strength And Transmitting Data During A Single Time Frame

US Patent:
6757261, Jun 29, 2004
Filed:
Aug 22, 2000
Appl. No.:
09/643275
Inventors:
Christian Volf Olgaard - Sunnyvale CA
Steve Yeung - Fremont CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04J 300
US Classification:
370280, 370345, 370336, 370509, 455450
Abstract:
A Global System for Mobile (GSM) cellular system transceiver with time division duplexed operations for receiving a data signal, monitoring received signal strength and transmitting a data signal during a single time frame. Multiple data registers are used to store the phase lock loop (PLL) frequency control data, e. g. , during the last time slot (slot ) of the prior time frame (or elsewhere in the prior time frame where time permits). Also during slot of the prior time frame, the PLL is programmed using the first data set for the data reception operation to be performed during one or more of the initial time slots (e. g. , time slots ) of the present time frame. During the next time slot (e. g. , slot ), the PLL is programmed using the second data set for the signal strength monitoring operation to be performed during that same time slot. During the next time slot (e. g.

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