Trong V Nguyen, 38Leander, TX

2013028, Oct 31, 2013

Apr 26, 2012

13/456217

Nitin Pant - New Delhi, IN
Trong D. Nguyen - Austin TX, US
Samaksh Sinha - Singapore, SG

FREESCALE SEMICONDUCTOR, INC. - Austin TX

G11C 7/10
H03K 5/22

36518905, 327 65

A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

5917356, Jun 29, 1999

Sep 11, 1995

8/526395

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX

International Business Machines Corp. - Armonk NY

H03K 300

327236

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

5524035, Jun 4, 1996

Aug 10, 1995

8/513245

Humberto F. Casal - Austin TX
Rafey Mahmud - Austin TX
Trong Nguyen - Houston TX
Mark L. Shulman - Staatsburg NY
Nandor G. Thoma - Plano TX

International Business Machines Corporation - Armonk NY

H03K 2100

377 47

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

5619158, Apr 8, 1997

Aug 18, 1995

8/516704

Humberto F. Casal - Austin TX
Joel R. Davidson - Austin TX
Hehching H. Li - Austin TX
Yuan C. Lo - Austin TX
Trong D. Nguyen - Webster TX
Campbell H. Snyder - Austin TX
Nandor G. Thoma - Plano TX

International Business Machines Corp. - Armonk NY

H03K 513

327292

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

5672991, Sep 30, 1997

Apr 15, 1996

8/632184

Nandor Gyorgy Thoma - Plano TX
Trong Duc Nguyen - Austin TX

International Business Machines Corporation - Armonk NY

H03H 1116

327239

A signal delay device is provided which enhances noise immunity by using a differential circuit, but also maintains the phase of the input clock signals. This device will also correct the phase of clock signals which are input to the delay device in an out of phase condition. The present invention is a delay circuit that includes functionally connecting each of the output signals with each of the input signals. Thus, the output signals are dependent on the same input and the steady state condition is the point where the leading edge of a first output signal intersects the trailing edge of a second output signal at the point which corresponds to one half of the pulse height of both signals. Since the signals are complements of one another, they will cross at 50% of their pulse height when they are "in phase". Thus, the present invention will maintain "in phase" input signals and seek an "in phase" condition for signals that are input to the delay circuit which are "out of phase".

5822596, Oct 13, 1998

Nov 6, 1995

8/554206

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX
Nandor Gyorgy Thoma - Plano TX

International Business Machines Corporation - Armonk NY

H03K 2100
G06F 1300

39575004

During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

2015024, Aug 27, 2015

Feb 24, 2014

14/187450

Dzung T. Tran - Austin TX, US
Trong D. Nguyen - Austin TX, US

H03K 17/22
G01R 19/00

Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations.