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Jun N Zeng, 60Eagan, MN

Related to:
Jia Li 53 Xiaohua Li Hongmin Li 56

Jun Zeng Phones & Addresses

Eagan, MN   

Burnsville, MN   

Monterey Park, CA   

334 Atlantic Blvd, Alhambra, CA 91801    626-2892461   

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Jun Zeng Photo 32

Jun Zeng

Jun Zeng Photo 33

Jun Zeng - Boulder, CO

Work:
Activia Networks - Montral, QC Jul 2008 to Apr 2011
Software Quality Engineer Trading Technologies International, Inc - Chicago, IL Oct 2005 to Jun 2007
Associate Quality Engineer University of Minnesota Sep 2001 to Aug 2004
Research Assistant Parametric Technology Corporation - Arden Hills, MN Aug 2003 to Jan 2004
Intern Three Gorges University Mar 2000 to Dec 2000
Network Administrator and Instructor Chongqing University Sep 1997 to Jan 2000
Research Assistant
Education:
University of Minnesota 2004
M.S. in Computer Engineering Chongqing University 2000
M.S. in Solid Mechanics Chongqing University 1997
B.S. in Engineering Mechanics
Jun Zeng Photo 34

Jun Zeng - Irvine, CA

Work:
Microsemi Jul 2012 to 2000
ERP programmer/Analyst Paul's TV - Irvine, CA Jun 2011 to Jun 2012
Sr. Application Developer Full Scope West - San Jose, CA Nov 2006 to Apr 2007
Senior Technical Consultant, Customer Lead Developer EPartners, Inc - Aliso Viejo, CA Feb 2005 to Aug 2006
Sr. Axapta Developer Hitachi Consulting - Irvine, CA Sep 2004 to Feb 2005
Axapta Technical Consultant SCS, Inc - Santa Monica, CA Jul 2004 to Sep 2004
Axapta Developer Beijing Jewel Investment Group Mar 2002 to Apr 2004
Vice Manager Columbus IT Partners - Costa Mesa, CA Aug 2000 to Feb 2002
Axapta Developer Beijing Biotech Trade Incorporated Aug 1996 to Sep 1999
Director and Manager
Education:
Beijing Jiaotong University 1995
MS in Economics Beijing Jiaotong University 1991
BS in Electronic Engineering University of California at Irvine - Irvine, CA
Advanced Object-Oriented Technology

Publications & IP owners

Us Patents

Ultra Dense Trench-Gated Power-Device With The Reduced Drain-Source Feedback Capacitance And Miller Charge

US Patent:
6683346, Jan 27, 2004
Filed:
Mar 7, 2002
Appl. No.:
10/092692
Inventors:
Jun Zeng - Torrance CA
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 2976
US Classification:
257330, 257301, 257306, 257328, 257331, 257332
Abstract:
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Low Voltage High Density Trench-Gated Power Device With Uniformly Doped Channel And Its Edge Termination Technique

US Patent:
6784505, Aug 31, 2004
Filed:
May 3, 2002
Appl. No.:
10/138913
Inventors:
Jun Zeng - Torrance CA
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 2994
US Classification:
257397, 257347, 257287, 257493, 257401, 438589
Abstract:
Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N substrate can be terminated at the edge of the die.

Gate Pad Protection Structure For Power Semiconductor Device And Manufacturing Method Therefor

US Patent:
6828177, Dec 7, 2004
Filed:
Dec 30, 2002
Appl. No.:
10/334754
Inventors:
Jun Zeng - Torrance CA
Assignee:
Pyramis Corporation - Torrance CA
International Classification:
H01L 21332
US Classification:
438135, 438139, 438140
Abstract:
A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.

Low Forward Voltage Drop Schottky Barrier Diode And Manufacturing Method Therefor

US Patent:
6921957, Jul 26, 2005
Filed:
Dec 31, 2002
Appl. No.:
10/335022
Inventors:
Jun Zeng - Torrance CA, US
Assignee:
Pyramis Corporation - Torrance CA
Delta Electronics, Inc.
International Classification:
H01L029/72
US Classification:
257476, 257471, 257472, 257475, 438576, 438581
Abstract:
A new low forward voltage drop Schottky barrier diode and its manufacturing method are provided. The method includes steps of providing a substrate, forming plural trenches on the substrate, and forming a metal layer on the substrate having plural trenches thereon to form a barrier metal layer between the substrate and the surface metal layer for forming the Schottky barrier diode.

Method Of Making An Ultra Dense Trench-Gated Power Device With The Reduced Drain-Source Feedback Capacitance And Miller Charge

US Patent:
6929988, Aug 16, 2005
Filed:
Oct 1, 2003
Appl. No.:
10/678444
Inventors:
Jun Zeng - Torrance CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L029/80
US Classification:
438192, 438193, 438195, 438284
Abstract:
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Low Voltage High Density Trench-Gated Power Device With Uniformity Doped Channel And Its Edge Termination Technique

US Patent:
6946348, Sep 20, 2005
Filed:
Mar 5, 2004
Appl. No.:
10/795723
Inventors:
Jun Zeng - Torrance CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L021/336
US Classification:
438270, 438424
Abstract:
Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N substrate can be terminated at the edge of the die.

Ultra Dense Trench-Gated Power Device With The Reduced Drain-Source Feedback Capacitance And Miller Charge

US Patent:
7098500, Aug 29, 2006
Filed:
Jul 8, 2005
Appl. No.:
11/178215
Inventors:
Jun Zeng - Torrance CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 27/108
US Classification:
257302, 257242, 257328, 257332
Abstract:
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Low Voltage High Density Trench-Gated Power Device With Uniformly Doped Channel And Its Edge Termination

US Patent:
7633102, Dec 15, 2009
Filed:
Oct 2, 2007
Appl. No.:
11/866072
Inventors:
Jun Zeng - Torrance CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 27/088
US Classification:
257287, 257341, 257401, 257E21549, 257E29201
Abstract:
Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N substrate can be terminated at the edge of the die.

Possible Relatives

Elizabeth J Zeng  Fan F Zeng  Fei Zeng  Feng T Zeng  Guang Zeng  Guoqing Zeng  Hao O Zeng  Jun Kang  Jun A Lee  Jun J Li 

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