Zhichao J Zhang, 491522 W Musket Way, Chandler, AZ 85286

7889148, Feb 15, 2011

Dec 19, 2007

12/004310

Rodolfo Diaz - Phoenix AZ, US
Jeffrey Peebles - Phoenix AZ, US
Richard LeBaron - Phoenix AZ, US
Zhichao Zhang - Tempe AZ, US
Lorena Lozano-Plata - Alcalá de Henares, ES

Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ

H01Q 13/00

343785, 343786, 343772, 343773

A plane wave antenna including: a horn antenna; a waveguide at least partially inside the horn antenna, wherein the waveguide includes: a central dielectric slab increasing in width toward the horn antenna and with a first dielectric constant, an upper slab above the central dielectric slab with a second dielectric constant, and a lower slab below the central dielectric slab with the second dielectric constant; wherein the central dielectric slab has a substantially constant thickness less than a quarter of a wavelength at a highest frequency of operation of the plane wave antenna.

8025531, Sep 27, 2011

Dec 16, 2010

12/970663

Zhichao Zhang - Chandler AZ, US
Joshua D. Heppner - Chandler AZ, US
Kemal Aygun - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01R 13/648

43960705

A shielded socket and method of fabrication is described. In an embodiment, a socket is formed of a conductive polymer socket housing, and at least one conductive contact is in electrical contact with the conductive polymer socket housing. In an embodiment, a socket is formed of an insulative socket housing, and at least one conductive contact is in electrical contact with a conductive grid embedded within the insulative housing.

8508947, Aug 13, 2013

Oct 1, 2010

12/896579

Sanka Ganesan - Chandler AZ, US
Mohiuddin Mazumder - San Jose CA, US
Zhichao Zhang - Chandler AZ, US
Kemal Aygun - Chandler AZ, US

Intel Corporation - Santa Clara CA

H05K 1/00
H05K 7/00

361749, 174117 FF

An assembly of substrate packages interconnected with flex cables. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing detachable inter-package flex cable connection. The flex cable comprises a transmission region that includes a plurality of signal traces and a ground plane. A plurality of solder mask strips are disposed on the plurality of signals traces to provide anchoring for the signal traces. The solder mask strips intersect the signals traces. The exposed signal traces and the ground plane are coated with organic solderability preservative material. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

8643184, Feb 4, 2014

Oct 31, 2012

13/665741

Zhichao Zhang - Chandler AZ, US
Tolga Memioglu - Chandler AZ, US
Tao Wu - Chandler AZ, US
Kemal Aygun - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/48
H01L 23/52
H01L 29/40
H01L 23/04

257758, 257690, 257691, 257698, 257734, 257E23019, 257E23142

Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

2006016, Jul 20, 2006

Jan 18, 2005

11/037531

Matthew Angyal - Stormville NY, US
Alina Deutsch - Chappaqua NY, US
Ibrahim Elfadel - Ossining NY, US
Zhichao Zhang - Tempe AZ, US

International Business Machines Corporation - Armonk NY

G06F 17/50

703014000

Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

2010032, Dec 30, 2010

Jun 26, 2009

12/459082

Zhichao Zhang - Mesa AZ, US
Kemal Aygun - Chandler AZ, US
Guizhen Zheng - Phoenix AZ, US

H05K 1/11
H05K 3/10

174262, 29846

In integrated circuit packages, core vias are created to provide electrical connections between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods for forming a via in a packaging substrate and packaging substrates having core vias formed in the core substrate material. Methods for forma a core via in a packaging substrate in which a first hole is created through the core substrate and filled with a low permittivity filler material. A second co-axially aligned hole is then created in the low permittivity filler material wherein the second hole is smaller in diameter than the first hole. The second hole is then filled with conducting material to provide a conducting via through the core substrate material.

2012018, Jul 19, 2012

Mar 26, 2012

13/430233

Zhichao Zhang - Mesa AZ, US
Kemal Aygun - Chandler AZ, US
Guizhen Zheng - Phoenix AZ, US

H05K 3/10

29846

In integrated circuit packages, core vias are created to provide electrical connections between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods for forming a via in a packaging substrate and packaging substrates having core vias formed in the core substrate material. Methods for forma a core via in a packaging substrate in which a first hole is created through the core substrate and filled with a low permittivity filler material. A second co-axially aligned hole is then created in the low permittivity filler material wherein the second hole is smaller in diameter than the first hole. The second hole is then filled with conducting material to provide a conducting via through the core substrate material.

2022041, Dec 29, 2022

Jun 25, 2021

17/359178

- Santa Clara CA, US
Pooya Tadayon - Portland OR, US
Zhichao Zhang - Chandler AZ, US
Liang Zhang - Chandler AZ, US

Intel Corporation - Santa Clara CA

G02B 6/122
G02B 6/30

Techniques and mechanisms for optically coupling a photonic integrated circuit (PIC) chip to an optical fiber via a planar optical waveguide structure. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A planar optical waveguide structure, which is adjacent to the IECs, comprises a core which is optically coupled between the PIC chip and an array of optical fibers. In another embodiment, an edge of the PIC forms a stepped structure, wherein an upper portion of the stepped structure comprises the plurality of coplanar IECs, and a lower portion of the stepped structure extends past the plurality of coplanar IECs.