Aarti Gupta, 50New York, NY

6662323, Dec 9, 2003

Oct 25, 1999

09/425886

Pranav Ashar - Belle Mead NJ
Aarti Gupta - Princeton NJ

NEC Corporation - Tokyo

G01R 3128

714724, 714 5, 324528, 324759

A fast error diagnosis system and process for combinational verification is described. The system and process localizes error sites in a combinational circuit implementation that has been shown to be inequivalent to its specification. In the typical case, it is not possible to identify the error location exactly. The invention uses a diagnosis strategy of gradually increasing the level of detail in the analysis algorithm to ultimately derive a small list of potential error sites in a short time. The invention combines the use of simulation, Binary Decision Diagrams, and Boolean satisfiability in a novel way to achieve the goal. The previous approaches have been limited in that they have either been constrained to a specific error model unlike the present invention, or they are inefficient in comparison to the present invention. The present invention allows for the final set of error sites derived to be small, where that set contains the actual error sites, and is derived in a reasonable amount of time.

6975976, Dec 13, 2005

Oct 23, 2000

09/693976

Albert E. Casavant - Belle Mead NJ, US
Aarti Gupta - Princeton NJ, US
Pranav Ashar - Belle Mead NJ, US

NEC Corporation - Tokyo

G06F017/50

703 14, 703 15, 703 16, 716 4

Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is to generate property-specific testbenches that are targeted either at proving the correctness of a property or at finding a bug. It is based on performing property-specific analysis on iteratively less abstract models of the design in order to obtain interesting paths in the form of a Witness Graph, which is then targeted during simulation of the entire design. This testbench generation framework will form an integral part of a comprehensive verification system currently being developed.

7346486, Mar 18, 2008

Jan 21, 2005

11/040409

Franjo Ivancic - Jersey City NJ, US
Pranav N. Ashar - Belle Mead NJ, US
Malay Ganai - Plainsboro NJ, US
Aarti Gupta - Princeton NJ, US
Zijiang Yang - Northville MI, US

NEC Laboratories America, Inc. - Princeton NJ

G06F 9/45
G06F 7/60
G06F 9/44
G06F 11/00

703 22, 703 2, 717124, 717141, 714 38

A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.

7930659, Apr 19, 2011

Jun 3, 2006

11/422069

Franjo Ivancic - Jersey City NJ, US
Aarti Gupta - Princeton NJ, US
Malay Ganai - Plainsboro NJ, US
Himanshu Jain - Pittsburgh PA, US

NEC Laboratories America, Inc. - Princeton NJ

G06F 17/50

716100

A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.

2004003, Feb 12, 2004

Jun 24, 2003

10/601648

Pranay Ashar - Belle Mead NJ, US
Aarti Gupta - Princeton NJ, US

NEC CORPORATION

G01R031/28

714/724000

A fast error diagnosis system and process for combinational verification is described. The system and process localizes error sites in a combinational circuit implementation that has been shown to be inequivalent to its specification. In the typical case, it is not possible to identify the error location exactly. The invention uses a diagnosis strategy of gradually increasing the level of detail in the analysis algorithm to ultimately derive a small list of potential error sites in a short time. The invention combines the use of simulation, Binary Decision Diagrams, and Boolean satisfiability in a novel way to achieve the goal. The previous approaches have been limited in that they have either been constrained to a specific error model unlike the present invention, or they are inefficient in comparison to the present invention. The present invention allows for the final set of error sites derived to be small, where that set contains the actual error sites, and is derived in a reasonable amount of time.