Ajit J Deora, 6745365 Rutherford Ter, Fremont, CA 94539

6353867, Mar 5, 2002

Jan 14, 2000

09/484111

Amjad Qureshi - Sunnyvale CA
Ajit J. Deora - Fremont CA
Ramana Kalapatapu - San Jose CA
Sagar Edara - San Jose CA

inSilicon Corporation - San Jose CA

G06F 1300

710129

Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or âbus wrapperâ. âPeripheralâ virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a âplug and playâ capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.

6816938, Nov 9, 2004

Mar 27, 2001

09/818429

Sagar Edara - San Jose CA
Amjad Qureshi - Fremont CA
Ajit Deora - Fremont CA
Ramana Kalapatapu - San Jose CA

Synopsys, Inc. - Mountain View CA

G06F 1314

710305, 710306, 710311, 710312, 710315

A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

5517626, May 14, 1996

Jan 29, 1993

8/011449

Jordan J. Archer - San Jose CA
Ajit J. Deora - San Jose CA
Kent S. Leung - Milpitas CA
Leon Peng - Mountain View CA
Robert C. Schopmeyer - Los Altos CA
David J. Scott - Gilroy CA
Sanjay Sharma - Sunnyvale CA
Virgil Stevens - Rounonent CA

S3, Incorporated - Santa Clara CA

G06F 1300

395290

An open high-speed local system bus for a microcomputer system which is decoupled from I/O and provides a consistent interface to the CPU subsystem, memory subsystem, graphics subsystem and peripheral subsystem. The local system bus supports discrete and burst transactions, pipelining in both the transactions, multiple microprocessor and distributed interrupts.

5752002, May 12, 1998

Jun 12, 1995

8/489654

Anand Naidu - San Jose CA
Ajit Deora - San Jose CA
Venkatesham Arunarthi - Sunnyvale CA

Sand Microelectronics, Inc. - San Jose CA

G06F 9455
G06F 1750

395500

A method and apparatus are provided for optimizing performance of a computer system component design by performance analysis of a simulation of the design. The method of the present invention comprises providing the computer system component design to an analyzing apparatus and carrying out a simulation run of the design. During the simulation run, operation data is generated cycle by cycle, and the generated operation data is collected and stored in a log file. The log file is input to a parser and the operation data is sequentially parsed to produce parsed data. Statistical calculations are then performed on the parsed data, and the performance results are output to the designer in graphical form. The performance information can be used to enhance performance of the computer system component prior to its fabrication.