Alan L Herrmann, 62890 Maranta Ave, Sunnyvale, CA 94087

6389558, May 14, 2002

Jul 6, 2000

09/610787

Alan L. Herrmann - Sunnyvale CA
Greg P. Nugent - Menlo Park CA

Altera Corporation - San Jose CA

G06F 1750

714 39, 714725, 714734, 702117, 716 4

A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer.

6408432, Jun 18, 2002

Apr 19, 2000

09/552575

Alan L. Herrmann - Sunnyvale CA
Timothy J. Southgate - Redwood City CA

Altera Corporation - San Jose CA

G06F 945

717139, 717124, 714725, 326 39

An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149. 1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

6460148, Oct 1, 2002

Jun 21, 2001

09/887918

Kerry Veenstra - San Jose CA
Krishna Rangasayee - Sunnyvale CA
Alan L. Herrmann - Sunnyvale CA

Altera Corporation - San Jose CA

G06F 1125

714 39, 714725, 714739, 703 16

Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory.

6614259, Sep 2, 2003

Mar 21, 2001

09/814458

Alan Herrmann - Sunnyvale CA

Altera Corporation - San Jose CA

H03K 19177

326 40, 326 46, 714725, 714726

A configuration memory for storing information which is in-system programmable. The programming of the configuration memory may be performed using JTAG (IEEE Standard 1149. 1) instructions. Furthermore, the configuration of a programmable logic device using the configuration data in the configuration memory may be initiated with a JTAG instruction. Pull-up resistors are incorporated within the configuration memory package.

6704889, Mar 9, 2004

Aug 6, 2002

10/212839

Kerry Veenstra - San Jose CA
Krishna Rangasayee - Sunnyvale CA
Alan L. Herrmann - Sunnyvale CA

Altera Corporation - San Jose CA

G06F 1125

714 39, 714725, 714739, 703 16

Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory.

7036046, Apr 25, 2006

Nov 14, 2002

10/295265

Nicholas James Rally - San Mateo CA, US
Alan Louis Herrmann - Sunnyvale CA, US

Altera Corporation - San Jose CA

G06F 11/00

714 39, 714725

User logic within a PLD is debugged by way of the hub. The PLD includes a serial interface (such as a JTAG port) that communicates with a host computer. Any number of client modules are within the PLD and provide instrumentation for the PLD. A module is a logic analyzer, fault injector, system debugger, etc. Each client module has connections with the user logic that allows the instrumentation to work with the user logic. The hub communicates with each client module over a hub/node signal interface and communicates with the serial interface over a user signal interface. The hub routes instructions and data from the host computer to a client module (and vice-versa) via the serial interface and uses a selection identifier to uniquely identify a module. The hub functions as a multiplexor, allowing any number of client modules to communicate externally though the serial interface as if each node were the only node interacting with user logic.

2012022, Sep 6, 2012

Mar 3, 2011

13/040255

David Samuel Goldman - Washington DC, US
Mark Bourgeault - Mississauga, CA
Vaughn Betz - Toronto, CA
Alan Louis Herrmann - Sunnyvale CA, US

Altera Corporation - San Jose CA

G06F 17/50

716128

A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

6134707, Oct 17, 2000

Jun 10, 1997

8/872652

Alan L. Herrmann - Sunnyvale CA
Timothy J. Southgate - Redwood City CA

Altera Corporation - San Jose CA

H03K 19177

717 5

An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149. 1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.