Alan F Norris, 657 Craftsfield Rd, Georgia, VT 05454

6658604, Dec 2, 2003

Oct 10, 2000

09/685939

William R. Corbin - Underhill VT
David P. Monty - Essex Junction VT
Erik A. Nelson - Waterbury VT
Alan D. Norris - Hinesburg VT
Steven W. Tomashot - Williston VT
David E. Chapman - Shelburne VT
Timothy E. Fiscus - South Burlington VT

International Business Machines Corporation - Armonk NY

G11B 2020

714700, 713400

To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.

6708298, Mar 16, 2004

Jan 23, 2001

09/768122

David P. Monty - Essex Junction VT
Erik A. Nelson - Waterbury VT
Alan D. Norris - Hinesburg VT
Steven W. Tomashot - Williston VT
David E. Chapman - Shelburne VT
Timothy E. Fiscus - South Burlington VT

International Business Machines Corporation - Armonk NY

G11C 2900

714702, 714718

A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e. g. , a DDR-type memory device) using the window strobe of a testing system.

7068564, Jun 27, 2006

Jun 29, 2003

10/604168

Mark D Jacunski - Colchester VT, US
Alan D Norris - Hinesburg VT, US
Samuel K Weinstein - Burlington VT, US

International Business Machines Corporation - Armonk NY

G11C 8/00

365233, 365194, 365203

A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

7194670, Mar 20, 2007

Feb 13, 2004

10/708184

Jonathan R. Fales - South Burlington VT, US
Gregory J. Fredeman - Staatsburg NY, US
Kevin W. Gorman - Fairfax VT, US
Mark D. Jacunski - Colchester VT, US
Toshiaki Kirihata - Poughkeepsie NY, US
Alan D. Norris - Hinesburg VT, US
Paul C. Parries - Wappingers Falls NY, US
Matthew R. Wordeman - Kula HI, US

International Business Machines Corp. - Armonk NY

G01R 31/28

714733, 714731

Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

7221601, May 22, 2007

Feb 28, 2006

11/363678

Mark D. Jacunski - Colchester VT, US
Alan D. Norris - Hinesburg VT, US
Samuel K. Weinstein - Burlington VT, US

International Business Machines Corporation - Armonk NY

G11C 7/00
H03H 11/26

365191, 365194, 327261, 327276

A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

7243276, Jul 10, 2007

Nov 6, 2003

10/605927

Alan D. Norris - Hinesburg VT, US
Samuel Weinstein - Cambridge MA, US
Stephan Wuensche - San Jose CA, US

International Business Machines Corporation - Armonk NY

G11C 29/00

714719, 714718, 365201

A DDR DRAM having a test mode and an operational mode and a method for testing the DDR DRAM. The method includes in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a band activate command to select and bring up a wordline selected for write of the DDR DRAM; (c) writing with auto-precharge, a test pattern to cells of the DDR DRAM; (d) repeating steps (b) and (c) until all wordlines for write have been selected; (e) issuing a bank activate command to select and bring up a wordline selected for read of the DDR DRAM; (f) reading with auto-precharge, the stored test pattern from cells of the DDR DRAM; and (g) repeating steps (c) and (f) until all wordlines for read have been selected.

7463548, Dec 9, 2008

Mar 19, 2007

11/687694

Alan D. Norris - Hinesburg VT, US
Samuel Weinstein - Cambridge MA, US
Stephan Wuensche - San Jose CA, US

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

G11C 8/16

36523313, 36523318, 3652331, 365203

A DDR DRAM having a test mode and an operational mode and a method for testing the DDR DRAM. The method includes in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a bank activate command to select and bring up a wordline selected for write of the DDR DRAM; (c) writing with auto-precharge, a test pattern to cells of the DDR DRAM; (d) repeating steps (b) and (c) until all wordlines for write have been selected; (e) issuing a bank activate command to select and bring up a wordline selected for read of the DDR DRAM; (f) reading with auto-precharge, the stored test pattern from cells of the DDR DRAM; and (g) repeating steps (e) and (f) until all wordlines for read have been selected.

7675121, Mar 9, 2010

Oct 8, 2007

11/868564

Dinh Dang - Essex Junction VT, US
Thai Doan - Burlington VT, US
Jessica Anne Levy - Essex Junction VT, US
Max Gerald Levy - Essex Junction VT, US
Alan Frederick Norris - Fairfax VT, US
James Albert Slinkman - Montpelier VT, US

International Business Machines Corporation - Armonk NY

H01L 29/78

257377, 257412, 257413, 257347, 257774, 257E29156

A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.