BackgroundCheck.run
Search For

Albert J Crowley Deceased12118 Aster Rd, Philadelphia, PA 19154

Albert Crowley Phones & Addresses

12118 Aster Rd, Philadelphia, PA 19154    215-6375960   

Yardley, PA   

Mentions for Albert J Crowley

Albert Crowley resumes & CV records

Resumes

Albert Crowley Photo 15

Albert Crowley

Albert Crowley Photo 16

Albert Crowley

Location:
Greater Philadelphia Area
Industry:
Computer Software

Publications & IP owners

Us Patents

Phase-Locked Loop With Variable Gain And Bandwidth

US Patent:
4156855, May 29, 1979
Filed:
Jan 26, 1978
Appl. No.:
5/872563
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03B 304
US Classification:
331 1A
Abstract:
A phase locked loop includes a voltage-controlled oscillator, and a phase and frequency detector for comprising an input signal pulse wave with a pulse wave from the voltage-controlled oscillator, and for providing a frequency control voltage to the voltage-controlled oscillator. When the pulses overlap, a pulse comparison circuit in the phase and frequency detector produces a frequency "up" signal or a frequency "down" signal proportional to the correction necessary. When the pulses do not overlap, the pulse comparison circuit produces a "non-overlap" signal which effects a rapid frequency correction by causing a current pump in the phase and frequency detector to increase its output to a fixed maximum value, and by causing a loop filter to increase its bandwidth to a fixed maximum value.

Phase Locked Loop Frequency Synthesizer Including Fractional Digital Frequency Divider

US Patent:
4468632, Aug 28, 1984
Filed:
Nov 30, 1981
Appl. No.:
6/326152
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03L 718
US Classification:
331 14
Abstract:
An improvement in a frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S. sub. VCO of frequency F. sub. VCO, a divider for dividing F. sub. VCO in division cycles with each division cycle consisting of the division of F. sub. VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S. sub. N of frequency F. sub. N, where the division ratio is ##EQU1## and where N, Y, M and Z are integers, a reference signal generator for generating a reference signal S. sub. R of frequency F. sub. R, and a phase detector responsive to S. sub. N and S. sub. R to produce an output signal whose amplitude is representative of the phase therebetween. The improvement is a control circuit comprising logic for detecting and averaging the output signal from the phase detector during each division of F. sub. VCO in each division cycle to produce a d. c.

Fast Tuned Phase Locked Loop Frequency Control System

US Patent:
4528523, Jul 9, 1985
Filed:
Dec 20, 1982
Appl. No.:
6/451423
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - Princeton NJ
International Classification:
H03L 706
US Classification:
331 10
Abstract:
An improved circuit for rapidly locking the phase of a reference signal e. sub. r of frequency f. sub. r with the phase of a signal e. sub. VCO in a phase locked loop which comprises a voltage controlled oscillator (VCO) for generating the signal e. sub. VCO of frequency f. sub. VCO, a divide-by-N circuit, for dividing f. sub. VCO by a variable N, a frequency/phase detector responsive to the phases of e. sub. VCO and e. sub. r to supply a control signal e. sub. c to the VCO, a loop filter circuit comprising a resistor and a capacitor for filtering e. sub. c, and logic for changing N to a new value N' in a time interval not less than T. Also provided is a circuit responsive to each change of N for coarse tuning the control signal supplied to the VCO and comprising a voltage generator responsive to each new value N' of N for generating a coarse tuned voltage having a magnitude which, when applied across the capacitor, will change the frequency f. sub. VCO /N to f. sub. VCO /N' to approximate f. sub. r.

Pulse Wave Phase And Frequency Detector

US Patent:
4105947, Aug 8, 1978
Filed:
Sep 16, 1977
Appl. No.:
5/833750
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03B 304
US Classification:
331 1A
Abstract:
A phase and frequency detector includes a first flip-flop triggered by a pulse wave from a reference source, and a second flip-flop triggered by a pulse wave from a voltage-controlled oscillator. Gate means couple outputs of the flip-flops back to reset inputs of the flip-flops so that one of the flip-flops generates pulses having widths proportional to the phase difference of the first and second pulse waves. The gate means inhibits the resetting of the triggered flip-flop when the pulses of the first and second pulse waves do not overlap, so that the triggered flip-flop then generates a continuous output useful for rapidly correcting the frequency of the voltage-controlled oscillator.

Precise Digitally Programmed Frequency Source

US Patent:
4349887, Sep 14, 1982
Filed:
Aug 22, 1980
Appl. No.:
6/181086
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03B 1900
US Classification:
364703
Abstract:
A digitally controlled oscillator for generating a plurality of signals spaced apart by very small frequency increments. The system comprises first means for generating a source signal of frequency f. sub. c, second means responsive to said first signal to produce a first binary output signal of frequency Nf. sub. c /2. sup. n, where n is a variable integer. Also provided are first frequency divider means responsive to said first binary output signal to produce a second binary output signal of frequency Nf. sub. c /2. sup. n+m, where m is another integer and second frequency divider means also responsive to said first signal f. sub. c to produce a third binary output signal of frequency f. sub. c /2. sup. T. Further provided are logic means responsive to said second and third binary output signals to produce a fourth binary output signal of average frequency f. sub. c /2. sup. T +Nf. sub. c /2. sup. n+m.

Frequency Synthesizer Using An Arithmetic Frequency Synthesizer And Plural Phase Locked Loops

US Patent:
4516084, May 7, 1985
Filed:
Feb 18, 1983
Appl. No.:
6/467644
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - Princeton NJ
International Classification:
H03L 700
US Classification:
331 2
Abstract:
A frequency synthesizer for controlling the frequency f. sub. 0 of a signal e. sub. 0 in response to a control signal e. sub. c2 to produce a band of selectable frequencies separated by. DELTA. f between the frequencies f. sub. x and f. sub. y, where (f. sub. x +R. DELTA. f)=f. sub. 0 and R is zero or any integer. ltoreq. (f. sub. y -f. sub. x)/. DELTA. f. The invention includes a first generator for generating the signal e. sub. 0, a second generator for generating a signal e. sub. 1 having a band of selectable frequencies separated by. delta. f, where. delta. f>>. DELTA. f, a frequency subtractor for subtracting f. sub. 1 from f. sub. 0 to produce a signal e. sub. 2 of frequency f. sub. 2. Also provided is a third generator for generating a variable preliminary reference signal of frequency f. sub. pr consisting of a band of selectable frequencies separated by M. DELTA.

Phase Frequency Detector Using Shift Register

US Patent:
4459559, Jul 10, 1984
Filed:
Nov 30, 1981
Appl. No.:
6/326141
Inventors:
Albert T. Crowley - Somerdale NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03D 1300
H03L 718
US Classification:
331 1A
Abstract:
An improvement in a phase locked loop comprising a VCO for generating a signal S. sub. VCO of frequency f. sub. VCO, a divider for dividing f. sub. VCO to produce a signal S. sub. N of frequency f. sub. N, a reference signal generator for generating a reference signal S. sub. R of frequency f. sub. R, and with said VCO responsive to a particular value E. sub. c of a variable control signal e. sub. c to cause f. sub. N =f. sub. R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S. sub. N and S. sub. R to cause f. sub. N =f. sub. R and comprising a three stage left/right shift register responsive to one of signals S. sub. N or S. sub. R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S. sub. N or S. sub. R to shift binary 1's into the third stage thereof in the left direction.

Universal Digital Frequency Synthesizer Using Single Side Band Techniques

US Patent:
4464638, Aug 7, 1984
Filed:
Nov 30, 1981
Appl. No.:
6/326136
Inventors:
Albert T. Crowley - Somerdale NJ
Robert M. Lisowski - Cherry Hill NJ
Assignee:
RCA Corporation - New York NY
International Classification:
H03L 718
US Classification:
331 1A
Abstract:
An improvement in a digital frequency synthesizer comprising a voltage-controlled oscillator (VCO) for producing a signal S. sub. VCO having a frequency f. sub. VCO, a first signal generator for generating a plurality of signals S. sub. AS having a spectrum of frequencies f. sub. AS, all exceeding a given minimum frequency f. sub. M, a mixer responsive to S. sub. VCO and to S. sub. AS to produce an output signal having a frequency (f. sub. VCO. +-. f. sub. AS), a divide-by-N divider responsive to (f. sub. VCO. +-. f. sub. AS) to produce a signal S. sub. N having a frequency f. sub. N, a second signal generator for generating a first reference signal S. sub. R1 having a frequency f. sub. R1, a phase detector responsive to S. sub. N and S. sub. R1 to produce a d. c.

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.