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Alexander T Chu, 40967 Belmont Ter UNIT 4, Sunnyvale, CA 94086

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967 Belmont Ter UNIT 4, Sunnyvale, CA 94086   

Vista, CA   

Urbana, IL   

San Francisco, CA   

Los Angeles, CA   

Fremont, CA   

San Jose, CA   

Santa Clara, CA   

2816 Menlo Ave APT 25, Los Angeles, CA 90007   

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Alexander Chu resumes & CV records

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Alexander Chu Photo 39

Alexander Chu

Alexander Chu Photo 40

Student At San Diego State University-California State University

Location:
Greater San Diego Area
Industry:
Retail
Education:
San Diego State University-California State University 2006 - 2011
Alexander Chu Photo 41

Alexander Chu

Location:
United States
Alexander Chu Photo 42

Alexander Chu

Location:
United States
Alexander Chu Photo 43

Alexander Chu - Cupertino, CA

Work:
Apple - Sunnyvale, CA Oct 2014 to Nov 2014
Data Entry Clerk
Hightail - Campbell, CA Jul 2014 to Sep 2014
Customer Service Representative
Wuxi Contact Electronics Co., Ltd. - Wuxi, Jiangsu, China Jun 2013 to Jun 2014
Account Representative
Genepharm, Inc. - Sunnyvale, CA Jan 2013 to Apr 2013
Business Development Associate (Internship)
Education:
San Diego State University - San Diego, CA 2012
Bachelor of Arts in Social Science
Alexander Chu Photo 44

Alexander Chu - Ithaca, NY

Work:
Fjord Ventures - Laguna Hills, CA Jan 2014 to Jun 2014
Metronom Health Intern
Biomedical Engineering Society Design Team Oct 2013 to Jun 2014
3D Sugar Printer Team Leader
Graduate Institute of Biomaterials and Tissue Engineering Jun 2013 to Sep 2013
Taiwan Tech Trek Intern
Undergraduate Research Opportunity Program (UROP) Nov 2011 to Sep 2012
Reel Team Lead
Education:
Cornell University 2015
Biomedical Engineering M.E
University of California - Irvine, CA 2009 to 2014
B.S. in Biomedical Engineering B
Skills:
Lean Six Sigma Black Belt (Cornell Certificate), Innovation & Commercialization (MITx certified), LabVIEW, MATLAB, SolidWorks Modeling, PCR, micro-dissection<br/>Languages... Mandarin Chinese (Conversational)
Alexander Chu Photo 45

Alexander Chu - Pasadena, CA

Work:
Art Institute of Hollywood - North Hollywood, CA Mar 2012 to Dec 2012
Assistant Director of Admissions
RadioShack - Agoura Hills, CA Oct 2006 to Oct 2011
Sales Associate
Education:
California State University Northridge Dec 2011
Bachelors of Science in Marketing

Publications & IP owners

Us Patents

Voltage Generator To Compensate Sense Amplifier Trip Point Over Temperature In Non-Volatile Memory

US Patent:
2011011, May 19, 2011
Filed:
Nov 13, 2009
Appl. No.:
12/617860
Inventors:
Fanglin Zhang - Fremont CA, US
Jong Park - Campbell CA, US
Man Mui - Santa Clara CA, US
Alexander Chu - San Francisco CA, US
Seungpil Lee - San Ramon CA, US
International Classification:
G11C 16/06
US Classification:
36518521
Abstract:
In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.

Compact High Speed Sense Amplifier For Non-Volatile Memory

US Patent:
2014000, Jan 2, 2014
Filed:
Nov 13, 2012
Appl. No.:
13/675781
Inventors:
Jongmin Park - Cupertino CA, US
Hao Thai Nguyen - San Jose CA, US
Juan Carlos Lee - Sunnyvale CA, US
Seungpil Lee - San Ramon CA, US
Alexander Tsang-nam Chu - San Francisco CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G11C 16/26
US Classification:
36518521
Abstract:
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level.

Methods, Systems, And Devices For Deploying An Implant

US Patent:
2021035, Nov 18, 2021
Filed:
May 11, 2021
Appl. No.:
17/317568
Inventors:
- Santa Clara CA, US
Scott C. Mosher - San Francisco CA, US
Gabriel R. Gonzales - Milpitas CA, US
Dylan Thomas Van Hoven - San Carlos CA, US
Alexander Chu - Diamond Bar CA, US
Erik Ross Jagger - Redwood City CA, US
International Classification:
A61F 2/24
Abstract:
A fastening system and a deployment system for controlling translation and rotation of a deployment device are presented. A fastening system may comprise one or more components configured for arresting or restricting translation of a delivery catheter of a medical device, including a mitral valve fixation device such as the MitraClip. A deployment system may comprise one or more components configured for locking rotation of a crimping cam to a slider to control deployment of a mitral valve fixation device.

Clip Removal Systems And Methods

US Patent:
2021034, Nov 11, 2021
Filed:
May 3, 2021
Appl. No.:
17/306407
Inventors:
- Santa Clara CA, US
Gabriel R. Gonzales - Milpitas CA, US
Alexander Chu - Diamond Bar CA, US
Richard Thomas Childs - San Francisco CA, US
International Classification:
A61B 17/128
A61B 17/3205
A61M 25/01
A61B 18/14
Abstract:
A system configured to detach an interventional implant from a cardiac valve includes a guide catheter and a capture mechanism routable through the guide catheter. The capture mechanism comprises a capture hypotube with a container portion/space configured to receive an interventional implant connected to cardiac valve tissue. The capture mechanism also includes a cutting arm axially moveable relative to the capture hypotube. The capture hypotube and the cutting arm each include cutting elements that are brought together upon actuation of the cutting arm to thereby cut the cardiac valve tissue surrounding the interventional implant to free the implant from the cardiac valve.

Medical Device Delivery System With Locking System

US Patent:
2021013, May 13, 2021
Filed:
Nov 6, 2020
Appl. No.:
17/091881
Inventors:
- Santa Clara CA, US
Gabriel Gonzales - Milpitas CA, US
Dylan Van Hoven - San Carlos CA, US
Alexander Chu - Diamond Bar CA, US
Erik Jagger - Redwood City CA, US
Scott Mosher - San Francisco CA, US
Assignee:
EVALVE, INC. - Santa Clara CA
International Classification:
A61F 2/24
A61B 17/00
Abstract:
Medical device delivery system including a catheter, handle, lock line handle, and lock line. The catheter includes a proximal end portion and a distal end portion. The handle is coupled to the proximal end portion of the catheter. The lock line handle is releasably coupled to the handle and actuatable between a lock position and an unlock position. The lock line includes a first end portion fixedly coupled to the lock line handle, a second end portion releasably coupled to the lock line handle, and an intermediate portion configured to be releasably coupled to the medical implant disposed proximate the distal end portion of the catheter. Actuating the lock line handle from the lock position toward the unlock position increases tension on the lock line, and actuating the lock line handle from the unlock position toward the lock position decreases tension on the lock line.

Stabilizer For A Medical Delivery System

US Patent:
2021012, May 6, 2021
Filed:
Nov 5, 2020
Appl. No.:
17/090167
Inventors:
- Santa Clara CA, US
Alexander C. Chu - Diamond Bar CA, US
Richard Childs - San Francisco CA, US
Dylan Van Hoven - San Carlos CA, US
Gabriel Gonzales - Milpitas CA, US
Assignee:
EVALVE, INC. - Santa Clara CA
International Classification:
A61F 2/24
Abstract:
Stabilizer for a medical delivery system is provided, wherein the medical delivery system has at least two portions translatable relative each other. The stabilizer includes a base and a sled coupled to the base. The sled includes a distal arm including a distal attachment for receiving a first portion of the medical delivery system, and a proximal arm including a proximal attachment for receiving a second portion of the medical delivery system. The sled is translatable relative to the base and the proximal attachment is translatable relative to the proximal arm.

Word Line Contact Regions For Three-Dimensional Non-Volatile Memory

US Patent:
2018019, Jul 12, 2018
Filed:
Jun 16, 2017
Appl. No.:
15/625848
Inventors:
- Plano TX, US
Alexander Chu - San Francisco CA, US
Kenneth Louie - Sunnyvale CA, US
Anirudh Amarnath - San Jose CA, US
Jixin Yu - Yokkaichi, JP
Yen-Lung Jason Li - San Jose CA, US
Tai-Yuan Tseng - Milpitas CA, US
Jong Yuh - Pleasanton CA, US
Assignee:
SanDisk Technologies LLC - Plano TX
International Classification:
G11C 8/08
G11C 5/06
H01L 27/112
G11C 8/10
G06F 13/40
Abstract:
Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Within-Array Through-Memory-Level Via Structures And Method Of Making Thereof

US Patent:
2017035, Dec 14, 2017
Filed:
Jun 8, 2016
Appl. No.:
15/176674
Inventors:
- Plano TX, US
Zhenyu LU - Milpitas CA, US
Alexander CHU - Milpitas CA, US
Kensuke YAMAGUCHI - Yokkaichi, JP
Hiroyuki OGAWA - Yokkaichi, JP
Daxin MAO - Cupertino CA, US
Yan LI - Milpitas CA, US
Johann ALSMEIER - San Jose CA, US
International Classification:
H01L 27/11582
H01L 27/11573
H01L 23/522
H01L 23/528
Abstract:
A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

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