Alfred Chan Cheong Chan, 63454 Tocoloma Ave, San Francisco, CA 94134

5010508, Apr 23, 1991

Feb 14, 1989

7/311294

Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Intel Corporation - Santa Clara CA

G06F 501
G06F 750

364748

In a floating-point subtraction of two numbers where a normalized result is needed, a prenormalization circuit predicts the number of leading zeroes which will appear in the resultant mantissa, due to the close value of the two source operands. The prenormalization circuit then causes appropriate left shifts of the two operand mantissas prior to the subtraction (two's complement addition) is performed, wherein the resultant mantissa will already be normalized.

4901270, Feb 13, 1990

Sep 23, 1988

7/248797

David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Intel Corporation - Santa Clara CA

G06F 750
G06F 752

364786

A four-to-two adder for adding four numbers and generating two numbers which has the same sum as the sum of the four input numbers is used to add partial products in a multiplier. A plurality of adder cells are arranged in parallel to process corresponding bits of the four numbers. Each adder cell couples three of the four input bits to the next stage. A four-bit parity circuit is used to control two multiplexers which select signals from a carry generator and the one input signal which is not coupled to the subsequent adder cell stage to provide two output bits corresponding to the two output numbers.

5027308, Jun 25, 1991

Feb 14, 1989

7/311296

Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Intel Corporation - Santa Clara CA

G06F 738
G06F 700

364748

In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa not to be normalized. A dual adder scheme is used to always provide a normalized result. One adder provides an unshifted result while the second adder provides a shifted result. A logic circuit looks for a carry out when performing addition and a bit value of the msb when performing subtraction to select the output from the adder providing the proper normalization. Rounding logic circuitry is used to predict the rounding of the resultant mantissa and carry bits are coupled as a carry-in to the adders to achieve the proper rounding in the same clock cycle as the adding/subtracting of the two mantissas.