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Alfred L Pan, 5444775 Aguila Ter, Fremont, CA 94539

Alfred Pan Phones & Addresses

249 Brunswick Pl, Fremont, CA 94539    510-2529294   

Alameda, CA   

San Francisco, CA   

Ann Arbor, MI   

Daly City, CA   

152 Lombard St APT 606P, San Francisco, CA 94111   

Work

Company: Pan, alfred Address: 44781 Aguila Terrace, Fremont, CA 94538 Phones: 510-2909002 Position: Partner Industries: Men's and Boys' Underwear and Nightwear

Mentions for Alfred L Pan

Publications & IP owners

Us Patents

Self-Aligned Common Carrier

US Patent:
6366468, Apr 2, 2002
Filed:
Apr 28, 2000
Appl. No.:
09/560943
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H05K 118
US Classification:
361761, 361760, 361783, 361782, 361768, 361811, 361820, 257723, 257724
Abstract:
Precision alignment of one or more parts on a common carrier is described. A self-aligned common carrier includes a carrier substrate having one or more pockets formed in the substrate. Each pocket includes a side profile formed in the pocket. A chip having an identical side profile that complements the side profile in the pocket is mounted to the carrier substrate by inserting the chip into the pocket. The complementary side profiles result in near perfect self-alignment between the chip and at least two orthogonal planes of the carrier substrate. The chip and the carrier substrate can be made from a single crystal semiconductor material and the side profiles can be formed by anisotropic etch process that selectively etches the chip and the substrate along a predetermined crystalline plane. The chip and the carrier substrate can be single crystal silicon having a (100) crystalline orientation and the side profiles can be formed by selectively etching the silicon along a (111) crystalline plane. The matching coefficients of thermal expansion between the chip and the carrier substrate substantially reduces thermal stress related interconnect failures and misalignment between the chip and the carrier substrate.

Chip-Carrier For Improved Drop Directionality

US Patent:
6443557, Sep 3, 2002
Filed:
Oct 29, 1999
Appl. No.:
09/430329
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Marshall Field - Corvallis OR
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
B41J 214
US Classification:
347 47, 347 63
Abstract:
A carrier frame having an aperture and a nozzle plate disposed on the carrier frame and positioned over the aperture is described. The nozzle plate has at least one nozzle formed between opposing surfaces of the nozzle plate. The carrier frame and the nozzle plate are made from materials having dissimilar thermal expansion coefficients such that the carrier frame has a thermal expansion coefficient that is less than the thermal expansion coefficient of the nozzle plate. The nozzle plate is staked to the carrier frame and then baked so that the nozzle plate shrinks during the baking process thereby becoming taught and under a state of tensile stress. The nozzle is formed in the nozzle plate after the baking process by laser ablation, for example. The nozzle thus formed has a true bore due to the taught nozzle plate and the opposed surfaces of the nozzle plate being parallel to each other. Consequently, a nozzle camber angle measured relative to a nozzle axis and defined by an angular displacement between a center point of symmetry on an input side of the nozzle and a center point of symmetry on an output side of the nozzle is coaxially aligned with the nozzle axis.

Self-Aligned Interconnect And Method For Producing Same

US Patent:
6457811, Oct 1, 2002
Filed:
Apr 30, 2001
Appl. No.:
09/843833
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Terry M. Lambright - Corvallis OR
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
B41J 214
US Classification:
347 50, 347 49
Abstract:
A self-aligned interconnect significantly reduces manufacturing costs and provides important advantages in a number of specific applications begins with a single crystal substrate. The substrate is machined to accept microelectronic chips at various locations (openings) along the substrate. Corresponding chips are constructed to precisely fit the openings in the crystal substrate. To ensure precision fit, both the substrate and the chip are etched along the same crystal plane. As a result, the chips can be placed in the openings in the substrate with perfect or nearly perfect alignment in the x and y directions without expensive alignment tools. In effect, the chips and the substrate are self aligned.

Three-Dimensional Interconnect System

US Patent:
6501663, Dec 31, 2002
Filed:
Feb 28, 2000
Appl. No.:
09/514484
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Assignee:
Hewlett Packard Company - Palo Alto CA
International Classification:
H01L 2352
US Classification:
361779, 361760, 361783, 361803, 174260, 257723, 257777, 257779, 257783, 22818022
Abstract:
A three-dimensional interconnect system is disclosed. The interconnect system electrically connects electrical devices that are disposed on different physical planes. The interconnect system includes a plurality of contiguously interconnected electrically conductive droplets such as solder ball droplets produced by a print-on-demand solder jet system. An interconnect is formed by repeatedly ejecting the conductive droplets along a predetermined path between components to be connected. Each ejected droplet is disposed adjacent to another ejected droplet to form a contiguously linked chain of droplets that bridge a physical gap between the components. A non-conductive coating can be deposited on the interconnect to protect the interconnect from damage and to encase the interconnect. The electrical resistance of the interconnect can be reduced by reflowing the droplets that form the interconnect, whereby the coating that encses the interconnect is operative to maintain the shape of the interconnect after reflow.

Hermetic Seal In Microelectronic Devices

US Patent:
6530649, Mar 11, 2003
Filed:
Aug 16, 2001
Appl. No.:
09/930228
Inventors:
Alfred I-Tsung Pan - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
B41J 205
US Classification:
347 56
Abstract:
A carrier includes a substrate formed to accept microelectronic chips at various pockets in the substrate. The microelectronic chips are hermetically sealed within the substrate by a deposition process using localized energy supplied at gaps between the chips and the pockets. During the heating process, seal material is deposited in the gaps to form the hermetic seals.

Self-Aligned Modules For A Page Wide Printhead

US Patent:
6533391, Mar 18, 2003
Filed:
Oct 24, 2000
Appl. No.:
09/695627
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Assignee:
Hewlett-Packard Development Company, LLP - Houston TX
International Classification:
H01L 2348
US Classification:
347 42, 257778
Abstract:
A system for precision self-alignment of multiple modules on an alignment substrate is disclosed. An alignment substrate includes a plurality of self-alignment features having a first profile formed in along a mounting surface thereof. A plurality of module substrates are mounted on the alignment substrate. Each module substrate includes an alignment key having a second profile formed along a base surface of the module substrate. The second profile of the alignment key complements the first profile of the self-alignment features. The module substrates are mounted on the alignment substrate by inserting their respective alignment keys into the self-alignment features so the alignment keys and the self-alignment features are connected in mating engagement with each other. As a result, the module substrates are positioned in near perfect self-alignment with each other with substantially no skew. The first profile and the second profile can be formed along a first crystalline plane and a second crystalline plane of the mounting and base surfaces respectively.

Actuator Apparatus, Process Of Forming Thereof And Method Of Actuation

US Patent:
6536875, Mar 25, 2003
Filed:
Jul 31, 2002
Appl. No.:
10/210607
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Assignee:
Hewlett-Packard Development Company - Houston TX
International Classification:
B41J 204
US Classification:
347 54
Abstract:
An actuator apparatus, process of forming thereof, and method of actuation are described in which a flexible member having opposing surface electrodes positioned between two substrates having opposing surface electrodes is caused to move by charging and discharging the opposing flexible member electrodes during first and second operative cycles.

Method Of Processing A Device By Electrophoresis Coating

US Patent:
6588095, Jul 8, 2003
Filed:
Apr 27, 2001
Appl. No.:
09/844377
Inventors:
Alfred I-Tsung Pan - Sunnyvale CA
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
H05B 306
US Classification:
29611, 298901, 29841, 29855, 204492, 204493, 204499, 204500, 347 57, 347 58
Abstract:
A method, and structure formed thereof, for processing an exposed conductive connection between an thermal inkjet head device and a flexible tape circuit connectable to control signals for driving the inkjet device. According to the method of processing, the exposed conductive connection is electrophoretically plated with a polymer to protect it against corrosive damage by coupling the exposed conductive connection to a first voltage potential and immersing it into an electrophoretic polymer solution in contact with an electrode at a second voltage potential thereby establishing a current between the electrode and the exposed connection such that the exposed connection is coated with a thin film of polymer of uniform thickness.

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