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Clarence W Teng, 715412 Glenshire Dr, Plano, TX 75093

Clarence Teng Phones & Addresses

5412 Glenshire Dr, Plano, TX 75093    972-8672725   

4301 Denver Dr, Plano, TX 75093    972-8672725    972-9851199   

Carrollton, TX   

Dallas, TX   

Grand Prairie, TX   

Lancaster, TX   

Mabank, TX   

Sunnyvale, CA   

5412 Glenshire Dr, Plano, TX 75093    214-4505394   

Social networks

Clarence W Teng

Linkedin

Work

Company: Carrollton plaza arts center 2006 Position: Owner

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Yale University

Languages

English

Industries

Semiconductors

Mentions for Clarence W Teng

Clarence Teng resumes & CV records

Resumes

Clarence Teng Photo 10

Chief Executive Officer

Location:
5412 Glenshire Dr, Plano, TX 75093
Industry:
Semiconductors
Work:
Carrollton Plaza Arts Center
Owner
Being Advanced Memory
Chief Executive Officer
Education:
Yale University
Doctorates, Doctor of Philosophy
Languages:
English

Publications & IP owners

Us Patents

Method For Fabricating A Multiple Well Structure For Providing Multiple Substrate Bias For Dram Device Formed Therein

US Patent:
5595925, Jan 21, 1997
Filed:
Apr 29, 1994
Appl. No.:
8/236745
Inventors:
Ih-Chin Chen - Richardson TX
Hisashi Shichijo - Plano TX
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2170
H01L 2700
US Classification:
437 52
Abstract:
A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Multiple Substrate Bias Random Access Memory Device

US Patent:
5894145, Apr 13, 1999
Filed:
Aug 12, 1997
Appl. No.:
8/909904
Inventors:
Ih-Chin Chen - Richardson TX
Hisashi Shichijo - Plano TX
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 27108
US Classification:
257296
Abstract:
A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Channel Stop Isolation Technology Utilizing Two-Step Etching And Selective Oxidation With Sidewall Masking

US Patent:
4538343, Sep 3, 1985
Filed:
Jun 15, 1984
Appl. No.:
6/620995
Inventors:
Gordon P. Pollack - Richardson TX
Clarence Teng - Plano TX
William R. Hunter - Garland TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2131
H01L 2176
US Classification:
29576W
Abstract:
A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Dram Cell And Method

US Patent:
4916524, Apr 10, 1990
Filed:
Jan 23, 1989
Appl. No.:
7/300467
Inventors:
Clarence W. Teng - Plano TX
Robert R. Doering - Plano TX
Ashwin H. Shah - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2978
H01L 2906
H01L 2702
US Classification:
357 236
Abstract:
The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Through-Field Implant Isolated Devices And Method

US Patent:
4987093, Jan 22, 1991
Filed:
Oct 24, 1989
Appl. No.:
7/426824
Inventors:
Clarence W. Teng - Plano TX
Roger A. Haken - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21265
H01L 2176
US Classification:
437 69
Abstract:
Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Oxide-Isolated Source/Drain Transistor

US Patent:
5043778, Aug 27, 1991
Filed:
Aug 25, 1988
Appl. No.:
7/238978
Inventors:
Clarence W. Teng - Dallas TX
Thomas E. Tang - Plano TX
Che-Chia Wei - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2978
H01L 2702
H01L 2904
H01L 2712
US Classification:
357 233
Abstract:
A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Trench Isolation Process

US Patent:
5061653, Oct 29, 1991
Filed:
Oct 30, 1990
Appl. No.:
7/605818
Inventors:
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2176
US Classification:
437 67
Abstract:
The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysilicon. The exposed silicon on the substrate and adjacent polysilicon are than oxidized to form the field oxide which is continuous, disposed above and contacts the remaining sidewall insulator in the trench.

Through-Field Implant Isolated Devices And Method

US Patent:
4890147, Dec 26, 1989
Filed:
Apr 15, 1987
Appl. No.:
7/038388
Inventors:
Clarence W. Teng - Plano TX
Roger A. Haken - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01C 2977
US Classification:
357 2311
Abstract:
Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Public records

Vehicle Records

Clarence Teng

Address:
5412 Glenshire Dr, Plano, TX 75093
VIN:
5NMSH73E17H040454
Make:
HYUN
Model:
SANT
Year:
2007

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