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Allen L Chan, 6410290 Crystal Creek Cv E, Piperton, TN 38017

Known as:
Allen C Chan
Related to:
Shi N Chen Eddie F Chan 52

Allen Chan Phones & Addresses

10290 Crystal Creek Cv E, Collierville, TN 38017    901-2184200   

San Ramon, CA   

2249 Valley Edge Cv, Cordova, TN 38016    901-3857009   

Dublin, CA   

Shiloh, TN   

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Mentions for Allen L Chan

Career records & work history

Medicine Doctors

Allen K. Chan

Specialties:
General Surgery, Vascular Surgery
Work:
West Coast Surgical Specialists
28078 Baxter Rd STE 420, Murrieta, CA 92563
951-5669370 (phone) 951-2004401 (fax)
Education:
Medical School
University of California, San Francisco School of Medicine
Graduated: 1993
Procedures:
Abdominal Aortic Aneurysm, Varicose Vein Procedures, Appendectomy, Endarterectomy, Hernia Repair, Laparoscopic Appendectomy, Laparoscopic Gallbladder Removal, Lower Leg Amputation, Peripheral Vascular Bypass, Thromboendarterectomy of the Peripheral Arteries
Conditions:
Abdominal Aortic Aneurysm, Appendicitis, Arterial Thromboembolic Disease, Breast Disorders, Cholelethiasis or Cholecystitis, Hemorrhoids, Inguinal Hernia, Intestinal Obstruction, Ischemic Bowel Disease, Thoracid Aortic Aneurysm, Varicose Veins
Languages:
English, Spanish
Description:
Dr. Chan graduated from the University of California, San Francisco School of Medicine in 1993. He works in Murrieta, CA and specializes in General Surgery and Vascular Surgery. Dr. Chan is affiliated with Inland Valley Medical Center, Loma Linda University Medical Center, Menifee Valley Medical Center and Temecula Valley Hospital.
Allen Chan Photo 1

Allen Wai Lun Chan

Specialties:
Family Medicine
Education:
East Carolina University (1999)

Publications & IP owners

Us Patents

Serial Communications Data Path With Optional Features

US Patent:
7356756, Apr 8, 2008
Filed:
Aug 20, 2004
Appl. No.:
10/923376
Inventors:
Allen Chan - Fremont CA, US
Faisal Dada - Ottawa, CA
Karl Lu - Nepean, CA
Bryon Moyer - Cupertino CA, US
Venkat Yadavalli - Santa Clara CA, US
Arye Ziklik - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03M 13/00
US Classification:
714781, 714798
Abstract:
Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

Flexible High-Speed Serial Interface Architectures For Programmable Integrated Circuit Devices

US Patent:
7602212, Oct 13, 2009
Filed:
Sep 24, 2007
Appl. No.:
11/904003
Inventors:
Allen Chan - San Jose CA, US
Wilson Wong - San Francisco CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 7/38
H03K 19/173
US Classification:
326 37, 716 16
Abstract:
An integrated circuit (e. g. , a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc. ) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.

Transmitter With Multiple Phase Locked Loops

US Patent:
7821343, Oct 26, 2010
Filed:
Aug 27, 2008
Appl. No.:
12/229813
Inventors:
Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Weiqi Ding - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
331 2, 331 49, 331 16, 327147, 327156
Abstract:
A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL.

Techniques For Providing Option Conductors To Connect Components In An Oscillator Circuit

US Patent:
7834712, Nov 16, 2010
Filed:
Nov 25, 2008
Appl. No.:
12/277810
Inventors:
Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Ali Atesoglu - Milpitas CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03B 5/00
US Classification:
331177V, 331117 R
Abstract:
An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Signal Detect For High-Speed Serial Interface

US Patent:
7899649, Mar 1, 2011
Filed:
Mar 24, 2008
Appl. No.:
12/053884
Inventors:
Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Thungoc M. Tran - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Weiqi Ding - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 19/00
US Classification:
702189
Abstract:
Signal detection circuitry for a serial interface oversamples the input—i. e. , samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

High-Speed Serial Interface Circuitry For Programmable Integrated Circuit Devices

US Patent:
7924184, Apr 12, 2011
Filed:
Sep 24, 2007
Appl. No.:
11/904008
Inventors:
Allen Chan - San Jose CA, US
Wilson Wong - San Francisco CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03M 9/00
US Classification:
341100, 341101
Abstract:
An integrated circuit (e. g. , a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc. ) includes programmable circuitry and a channel of high-speed serial data signal interface (e. g. , transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

Techniques Relating To Oscillators

US Patent:
8035453, Oct 11, 2011
Filed:
Oct 12, 2009
Appl. No.:
12/577568
Inventors:
Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Simardeep Maangat - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 3/03
H03L 1/00
H03L 7/099
US Classification:
331 57, 331186, 327158, 327277, 327280
Abstract:
An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

Serial Communications Control Plane With Optional Features

US Patent:
8073040, Dec 6, 2011
Filed:
Aug 20, 2004
Appl. No.:
10/923540
Inventors:
Allen Chan - Fremont CA, US
Faisal Dada - Ottawa, CA
Karl Lu - Nepean, CA
Bryon Moyer - Cupertino CA, US
Venkat Yadavalli - Santa Clara CA, US
Arye Ziklik - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H04B 1/38
US Classification:
375219, 375216, 375224, 375238, 375222
Abstract:
A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Possible Relatives

Cynthia Chan  David C Chan  De C Chan  Deana M Chan  Dai C Chan  Deborah H Chan  Daniel S Chan  Allen J Johnson  Allen Stancil  Allen L Standley 

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