Allen T Chan, 54609 Carmel Ave, Albany, CA 94706

7356756, Apr 8, 2008

Aug 20, 2004

10/923376

Allen Chan - Fremont CA, US
Faisal Dada - Ottawa, CA
Karl Lu - Nepean, CA
Bryon Moyer - Cupertino CA, US
Venkat Yadavalli - Santa Clara CA, US
Arye Ziklik - Sunnyvale CA, US

Altera Corporation - San Jose CA

H03M 13/00

714781, 714798

Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

7821343, Oct 26, 2010

Aug 27, 2008

12/229813

Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Weiqi Ding - Fremont CA, US

Altera Corporation - San Jose CA

H03L 7/00

331 2, 331 49, 331 16, 327147, 327156

A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL.

7834712, Nov 16, 2010

Nov 25, 2008

12/277810

Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Ali Atesoglu - Milpitas CA, US

Altera Corporation - San Jose CA

H03B 5/00

331177V, 331117 R

An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

7899649, Mar 1, 2011

Mar 24, 2008

12/053884

Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Thungoc M. Tran - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Weiqi Ding - Fremont CA, US

Altera Corporation - San Jose CA

G06F 19/00

702189

Signal detection circuitry for a serial interface oversamples the input—i. e. , samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

8035453, Oct 11, 2011

Oct 12, 2009

12/577568

Wilson Wong - San Francisco CA, US
Allen Chan - San Jose CA, US
Simardeep Maangat - Sunnyvale CA, US

Altera Corporation - San Jose CA

H03K 3/03
H03L 1/00
H03L 7/099

331 57, 331186, 327158, 327277, 327280

An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

8073040, Dec 6, 2011

Aug 20, 2004

10/923540

Allen Chan - Fremont CA, US
Faisal Dada - Ottawa, CA
Karl Lu - Nepean, CA
Bryon Moyer - Cupertino CA, US
Venkat Yadavalli - Santa Clara CA, US
Arye Ziklik - Sunnyvale CA, US

Altera Corporation - San Jose CA

H04B 1/38

375219, 375216, 375224, 375238, 375222

A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

8161429, Apr 17, 2012

Aug 20, 2004

10/923477

Allen Chan - Fremont CA, US
Faisal Dada - Ottawa, CA
Karl Lu - Nepean, CA
Bryon Moyer - Cupertino CA, US
Samson Tan - San Francisco CA, US
Venkat Yadavalli - Santa Clara CA, US
Arye Ziklik - Sunnyvale CA, US

Altera Corporation - San Jose CA

G06F 17/50

716100, 716101, 716102

A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional serial communications link features are implemented are able to perform the lane polarity reversal and lane order reversal functions. Integrated circuits in which the optional serial communications link features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

8175143, May 8, 2012

Feb 26, 2008

12/037284

Wilson Wong - San Francisco CA, US
Tin H. Lai - San Jose CA, US
Allen Chan - San Jose CA, US
Tim Tri Hoang - San Jose CA, US

Altera Corporation - San Jose CA

H03H 7/30

375232, 375229, 375230, 375233, 375284, 375285, 375316, 375340, 375345, 375346, 375350, 708300

A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.