Alok Gupta, 665000 Libbie Ml Blvd East UNIT 534, Richmond, VA 23230

8401503, Mar 19, 2013

Feb 21, 2006

11/358996

Seong Taek Chung - Redwood City CA, US
Vinay Murthy - San Diego CA, US
Alok Kumar Gupta - Encinitas CA, US
Fuyun Ling - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H04B 1/18

4551822, 4555531, 455136, 455259

Techniques for performing frequency control using dual-loop automatic frequency control (AFC) are described. The dual-loop AFC includes an inner loop that corrects short-term frequency variations (e. g. , due to Doppler effect) and an outer loop that corrects long-term frequency variations (e. g. , due to component tolerances and temperature variations). In one design, a first inner loop is implemented for frequency control of a first system (e. g. , a broadcast system), a second inner loop is implemented for frequency control of a second system (e. g. , a cellular system), and at least one outer loop is implemented for adjusting a reference frequency used to receive signals from the first and second systems. Each inner loop estimates and corrects the frequency error in an input signal for the associated system and may be enabled when receiving the input signal from the system. The reference frequency may be used for frequency downconversion, sampling and/or other purposes.

8407441, Mar 26, 2013

May 19, 2011

13/111446

Thomas J. Giovannini - San Jose CA, US
Alok Gupta - Fremont CA, US
Ian Shaeffer - Los Gatos CA, US
Steven C. Woo - Saratoga CA, US

Rambus Inc. - Sunnyvale CA

G06F 12/00

711167, 711100, 711154, 711170

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

2009016, Jun 25, 2009

Mar 17, 2008

12/049928

Thomas J. Giovannini - San Jose CA, US
Alok Gupta - Fremont CA, US
Ian Shaeffer - Los Gatos CA, US
Steven C. Woo - Saratoga CA, US

RAMBUS INC. - Los Altos CA

G11C 7/22

365193, 365194

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

2010007, Mar 18, 2010

Sep 10, 2009

12/557284

Alok Kumar GUPTA - Cupertino CA, US
Minwen JI - Los Altos CA, US
Timothy P. MANN - Palo Alto CA, US
Tahir MOBASHIR - Mountain View CA, US
Umit RENCUZOGULLARI - Sunnyvale CA, US
Ganesha SHANMUGANATHAN - Mountain View CA, US
Limin WANG - Sunnyvale CA, US
Anne Marie HOLLER - Los Altos CA, US

VMWARE, INC. - Palo Alto CA

G06F 1/32

713310, 713320

A method of reducing power consumption of a server cluster of host systems with virtual machines executing on the host systems is disclosed. The method includes recommending host system power-on when there is a host system whose utilization is above a target utilization, and recommending host system power-off when there is a host system whose utilization is below the target utilization. Recommending host system power-on includes calculating impact of powering on a standby host system with respect to reducing the number of highly-utilized host systems in the server cluster. The impact of powering on is calculated by simulating moving some virtual machines from highly utilized host systems to the standby host system being recommended to be powered on. Recommending host system power-off includes calculating impact of powering off a host system with respect to decreasing the number of less-utilized host systems in the server cluster. The impact of powering off is calculated by simulating moving all virtual machines from the host system, which is being recommended to be powered-off, to less-utilized host systems.

2013005, Feb 28, 2013

Aug 31, 2011

13/223004

Alok GUPTA - Fremont CA, US
Barry A. Wagner - San Jose CA, US

G06F 12/06

711105, 711E12078

A memory controller and a dynamic random access memory (DRAM) interface are disclosed. The memory controller implements signals for the DRAM interface. The DRAM interface includes a differential clock signal, an uncalibrated parallel command bus, and a high-speed, serial address bus. The command bus may be used to initiate communication with the memory device upon power-up and to initiate calibration of the address bus.

2013010, Apr 25, 2013

Oct 21, 2011

13/279172

Alok Gupta - Fremont CA, US

NVIDIA Corporation - Santa Clara CA

G06F 12/00

711167, 711E12001

An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle.

2013015, Jun 13, 2013

Dec 9, 2011

13/316386

Alok Gupta - Fremont CA, US

NVIDIA CORPORATION - Santa Clara CA

G06F 12/00
G06F 13/12

711154, 710 71, 711E12001

A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial links using parallel links thereby reducing the number of links that need calibration. The method includes sending serialized data over a serial interface and receiving parallel data via a parallel interface. The serialized data is looped back via the parallel interface. The method further includes comparing the parallel data and the serialized data for a match thereof and calibrating the serial interface by adjusting the sending of the serialized data until the comparing detects the match. The adjusting of the sending is operable to calibrate the sending of the serialized data over the serial interface.

2013029, Nov 7, 2013

May 3, 2012

13/463717

Alok Gupta - Fremont CA, US

G06F 12/02

711105, 711E12002

One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port memory device over a single connection. Command and address information for each port of the multi-port memory device is time-multiplexed within the controller to produce a single stream of commands and addresses for different memory requests. The single stream of commands and addresses is transmitted by the controller to the multi-port memory device where the single stream is demultiplexed to generate separate streams of commands and addresses for each port of the multi-port memory device.