An My Huynh, 492714 Grange Crk Ct, Round Rock, TX 78665

7546451, Jun 9, 2009

Jun 19, 2002

10/174621

Chris Cicchetti - Menlo Park CA, US
Jean-François Dubé - Santa Clara CA, US
Thomas Andrew Myers - San Jose CA, US
An Huynh - Alameda CA, US
Geoffrey T. Hibbert - San Jose CA, US

Finisar Corporation - Sunnyvale CA

G06F 9/00

713100, 713 1, 713 2, 711 2, 711 5, 712206

A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a program segment and a hold segment. At startup, instructions are loaded into the hold segment, and the programmable device begins executing those instructions. While the hold segment instructions are executed, the program segment is loaded with instructions. Once the program segment is filled, control is shifted to it and instructions from this segment are executed by the programmable device. When the program segment has been executed, control is shifted back to the hold segment, and instructions are taken from it while the program segment is reloaded with a fresh set of instructions from the host application. Once the program segment is reloaded, control is redirected and execution of instructions from the program segment is continued.

2006020, Sep 7, 2006

Apr 24, 2003

10/422456

Paul Gentieu - Sunnyvale CA, US
Chris Cicchetti - Menlo Park CA, US
Arthur Lawson - Morgan Hill CA, US
An Huynh - Alameda CA, US
Harold Yang - Milpitas CA, US

G06F 11/00

714704000

An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.