Andrew T Cao, 603901 Riverbend Ter, Fremont, CA 94555

7453726, Nov 18, 2008

Jan 23, 2007

11/656609

Andrew Cao - Fremont CA, US
Ernes Ho - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

G11C 11/34
G11C 14/00

36518508, 365154, 36518505, 36518514, 365202

A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.

7602641, Oct 13, 2009

Sep 25, 2008

12/284890

Andrew Cao - Fremont CA, US
Ernes Ho - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

G11C 11/34
G11C 14/00

36518508, 365154, 36518505, 36518514, 365202

A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.

2015034, Dec 3, 2015

May 28, 2014

14/289483

- San Jose CA, US
Arkalgud R. Sitaram - Cupertino CA, US
Andrew Cao - Fremont CA, US
Bong-Sub Lee - Mountain View CA, US

H01L 25/065
H01L 21/768
H01L 21/56
H01L 23/48
H01L 23/373
H01L 23/367
H01L 23/29
H01L 23/31
H01L 25/00
H01L 23/00

A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.