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Andrew W Vogan, 58Austin, TX

Andrew Vogan Phones & Addresses

Austin, TX   

Gilroy, CA   

San Jose, CA   

1333 Indian Paintbrush, Longmont, CO 80503    303-7728558   

20383 Tremont Way, Beaverton, OR 97007    503-2592637   

Aloha, OR   

Layton, UT   

Lafayette, CO   

Boulder, CO   

768 Colleen Dr, San Jose, CA 95123    503-2592637   

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Andrew W Vogan

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Work

Company: Apple Sep 2019 Position: Senior principal engineer

Education

School / High School: Wright State University 1983 to 1988 Specialities: Computer Science

Skills

Firmware • Embedded Systems • Debugging • Soc • System Architecture • Sata • Ssd • Embedded Software • Hardware • Storage • Hard Drives • Asic • Rtl Design • Scsi • Arm • Semiconductors • C • Device Drivers • Verilog • Fpga • Hardware Architecture • Raid • Digital Signal Processors • Rtos • Intel • Processors • Logic Analyzer • I2C • Pcb Design • Logic Design • Pcie • Manufacturing • Failure Analysis • Vhdl • Xilinx • Assembly • Architecture • Kernel • Microcontrollers • Microprocessors • Ic • Usb • X86 • Computer Architecture • Firmware and Rtl Architect • Vcs • Dsp • Modelsim

Industries

Computer Hardware

Mentions for Andrew W Vogan

Andrew Vogan resumes & CV records

Resumes

Andrew Vogan Photo 31

Senior Principal Engineer

Location:
Gilroy, CA
Industry:
Computer Hardware
Work:
Apple
Senior Principal Engineer
Intel Corporation Jan 2005 - Jul 2011
Principal Engineer, Ssd Architect
Maxtor Jan 1999 - Jan 2005
Principal Engineer, Architect
Iomega Corp Jan 1995 - Jan 1999
Principal Engineer
Maxtor Jan 1994 - Aug 1995
Senior Staff Engineer
Cv Tech Jan 1989 - Jan 1994
Principal Engineer
Ohio Kache Systems Jan 1986 - Jan 1989
Design Engineer
Education:
Wright State University 1983 - 1988
Graham High School
Skills:
Firmware, Embedded Systems, Debugging, Soc, System Architecture, Sata, Ssd, Embedded Software, Hardware, Storage, Hard Drives, Asic, Rtl Design, Scsi, Arm, Semiconductors, C, Device Drivers, Verilog, Fpga, Hardware Architecture, Raid, Digital Signal Processors, Rtos, Intel, Processors, Logic Analyzer, I2C, Pcb Design, Logic Design, Pcie, Manufacturing, Failure Analysis, Vhdl, Xilinx, Assembly, Architecture, Kernel, Microcontrollers, Microprocessors, Ic, Usb, X86, Computer Architecture, Firmware and Rtl Architect, Vcs, Dsp, Modelsim

Publications & IP owners

Us Patents

Disk Drive That Refreshes Data On Portions Of A Disk Based On A Number Of Write Operations Thereto

US Patent:
7345837, Mar 18, 2008
Filed:
Jul 19, 2005
Appl. No.:
11/184273
Inventors:
Erhard Schreck - San Jose CA, US
Donald Brunnett - Pleasanton CA, US
Hung V. Nguyen - San Jose CA, US
Bruce Schardt - Tracy CA, US
Andrew Vogan - Longmont CO, US
Assignee:
Maxtor Corporation - Longmont CO
International Classification:
G11B 27/36
G11B 5/09
US Classification:
360 31, 360 53
Abstract:
A disk drive includes a rotatable data storage disk, a transducer, an actuator, and a controller. The transducer is configured to read and write data on the disk. The actuator is configured to position the transducer relative to defined portions of the disk. The controller is configured to determine how many times data has been written to the defined portions of the disk. The controller is also configured to refresh data residing at a particular one of the defined portions of the disk when the number of times data has been written to the particular defined portion of the disk satisfies a threshold value.

Methods And Structure For Patching Embedded Firmware

US Patent:
7596721, Sep 29, 2009
Filed:
Jan 9, 2004
Appl. No.:
10/755117
Inventors:
Lance Flake - Longmont CO, US
Andrew W. Vogan - Longmont CO, US
Assignee:
Maxtor Corporation - Scotts Valley CA
International Classification:
G06F 11/00
US Classification:
714 42
Abstract:
Methods and structures for providing patches or updates to embedded ROM firmware simply and inexpensively while avoiding imposition of execution or memory fetch overhead. A patch memory includes locations storing addresses and optional alternate data values. Read/fetch operations addressed to a firmware ROM memory are applied in parallel to the patch memory. All locations of the patch memory may be compared in parallel to the supplied address to determine if a match is found in patch memory. If no match is found, the read/fetch memory cycle completes normally retrieving data from the ROM memory. If a match is found, the alternate data value is applied to the data bus in place of the ROM memory data retrieved. Any ROM location may therefore be patched regardless of whether the location stores instruction or data.

Methods And Structure For Dynamic Multiple Indirections In A Dynamically Mapped Mass Storage Device

US Patent:
7603530, Oct 13, 2009
Filed:
Oct 19, 2006
Appl. No.:
11/583623
Inventors:
Bruce A. Liikanen - Berthoud CO, US
Mike L. Mallary - Sterling MA, US
Andrew W. Vogan - Portland OR, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711162, 711156, 711202, 711206
Abstract:
Methods and structures for dynamic multiple indirections to improve reliability and performance of a dynamically mapped storage devices. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide for dynamically altering the number of replicated copies (multiple mapped indirections) of user data stored on the storage device. Performance information regarding operation of the storage device may be gathered by the storage device controller such that where physical capacity of the storage device permits and as degrading reliability is detected, additional copies (multiple indirections) of stored user data may be written to the mapped storage device. Increased multiple indirections improves reliability by decreasing the probability of data loss in response to various failure modes of the storage device. Strategic physical placement of the multiple copies (multiple indirections) may improve performance by reducing latencies associated with accessing the user data.

Methods And Structure For Writing Lead-In Sequences For Head Stability In A Dynamically Mapped Mass Storage Device

US Patent:
7617358, Nov 10, 2009
Filed:
Oct 19, 2006
Appl. No.:
11/583502
Inventors:
Bruce A. Liikanen - Berthoud CO, US
Andrew W. Vogan - Portland OR, US
Assignee:
Seagate Technology, LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711112, 711158, 711170, 711202, 360 7808
Abstract:
Methods and structures for writing thermal lead-in sequences to provide head stability in a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide writing thermal lead-in sequences to allow the write head to stabilize. As the write head begins writing a sequence of data to the recordable media, the write head may not have a desired thermal stability. Thus, there may be thermal flux with some of the data, affecting the reliability of the data. Mapping features and aspects hereof allow the write head to write a thermal lead-in sequence of data that does not destroy valuable data, allowing the write head to begin writing before stabilizing. Writing the thermal lead-in sequence will cause the write head to warm up and become stable, and thus be ready to write valid data.

Methods And Structure For Dynamic Data Density In A Dynamically Mapped Mass Storage Device

US Patent:
7620772, Nov 17, 2009
Filed:
Oct 19, 2006
Appl. No.:
11/583331
Inventors:
Bruce A. Liikanen - Berthoud CO, US
Mike L. Mallary - Sterling MA, US
John Mead - Longmont CO, US
Eric D. Mudama - Longmont CO, US
John W. VanLaanen - Louisville CO, US
Andrew W. Vogan - Portland OR, US
Assignee:
Seagate Technology, LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711112, 711154, 711170, 711173, 711202
Abstract:
Methods and structures for dynamic density control to improve reliability of a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide for dynamically altering the recording density of user data stored on the storage device. So long as the physical capacity utilization of the storage device permits, new data stored on the device may be stored at lower density to improve reliability in reading back the recorded data. Further features and aspects hereof may reduce the recording density only for data deemed to be critical. Radial (track) density, longitudinal (bit) density, or both may be dynamically controlled to reduce recording density. As physical capacity utilization increases, data previously recorded at lower density may be migrated (re-recorded) at normal higher density.

Methods And Structure For Field Flawscan In A Dynamically Mapped Mass Storage Device

US Patent:
7653847, Jan 26, 2010
Filed:
Oct 19, 2006
Appl. No.:
11/583767
Inventors:
Bruce A. Liikanen - Berthoud CO, US
Eric D. Mudama - Longmont CO, US
John W. VanLaanen - Louisville CO, US
Andrew W. Vogan - Portland OR, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C 29/00
US Classification:
714723, 714 25, 714718, 714735, 714736, 714742, 714745, 714824, 714704, 714 42, 360 31, 360 53, 369 531, 369 5332, 369 5335
Abstract:
Methods and structures for performing field flawscan to reduce manufacturing costs of a dynamic mapped storage device. In a dynamic mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof permit flawscan testing of a storage device to be completed substantially concurrently with processing write requests for its intended application. A fraction of the storage device may be certified by an initial flawscan performed during manufacturing testing. Statistical sampling sufficient to assure a high probability of achieving specified capacity may be performed to reduce manufacturing time and costs in testing. Final flawscan of the remainder of the storage locations may be performed substantially concurrently with processing of write requests after the device is installed for its intended application. Mapping features and aspects hereof allow the storage device controller to perform flawscan and write operations concurrently.

Methods And Structure For Dynamic Appended Metadata In A Dynamically Mapped Mass Storage Device

US Patent:
7685360, Mar 23, 2010
Filed:
Oct 19, 2006
Appl. No.:
11/583341
Inventors:
Don Brunnett - Pleasanton CA, US
Bruce A. Liikanen - Berthoud CO, US
John Mead - Longmont CO, US
Eric D. Mudama - Longmont CO, US
John W. VanLaanen - Louisville CO, US
Andrew W. Vogan - Portland OR, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711112, 711156, 360 31
Abstract:
Methods and structures for appending metadata with recorded data in a dynamic mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof allow presently unused physical space to be used for storing additional metadata associated with recorded data. As the current capacity ratio of the storage device increases, appending of metadata may cease and previously recorded data including metadata may be re-recorded (migrated) to eliminate the appended metadata. The appended metadata may be used for enhanced diagnosis and analysis of characteristics of the operating storage device and may be used to restore the content of the storage device to an earlier state. The metadata may include, for example, track following position of the read/write head, temperature, head flying height, and time of day.

Disk Drives And Methods Allowing Configurable Zoning

US Patent:
7694071, Apr 6, 2010
Filed:
Jul 11, 2006
Appl. No.:
11/484341
Inventors:
Jasbir Sidhu - San Jose CA, US
Andrew Vogan - Aloha OR, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711112, 711114
Abstract:
A disk drive capable of being configured into a plurality of data storage zones, wherein some of the zones have different performance characteristics than other zones; a method for performing such a zoning configuration; and, a host device utilizing such a disk drive. The disk drive comprises a disk having a plurality of sectors for storing data, a head for reading and writing the data, and a disk drive controller for controlling the head, wherein the plurality of the sectors are organized into the plurality of zones. In one embodiment of the present invention, the performance characteristics of the zones are dictated by configuration settings in the disk drive controller. The configuration settings may include settings for a plurality of parameters. In some embodiments of the present invention, the plurality of parameters comprises a CCT (command completion time) parameter, a Write Verify parameter, a Write Continuous parameter, a Read Continuous parameter, and an Error Re-allocation parameter. In other embodiments of the present invention, the configuration settings may also include a group of addresses associated with each zone.

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