Andrew G Waterman, 54Seattle, WA

2023001, Jan 19, 2023

Jul 13, 2022

17/863826

- San Mateo CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/48
G06F 9/30
G06F 1/10
G06F 1/3296

Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

2021030, Sep 30, 2021

Apr 23, 2020

16/856462

- San Mateo CA, US
Krste Asanovic - Berkeley CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/30
G06F 9/38
G06F 9/48

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

2021025, Aug 19, 2021

May 3, 2021

17/306373

- San Mateo CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/30
G06F 9/38

Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

2020021, Jul 2, 2020

Aug 28, 2019

16/553839

- San Mateo CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/38
G06F 12/0875

Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

2020021, Jul 2, 2020

Mar 22, 2019

16/362121

- San Mateo CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/38
G06F 9/30

Systems and methods are disclosed for secure predictors for speculative execution. Some implementations may eliminate or mitigate side-channel attacks, such as the Spectre-class of attacks, in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a predictor circuit that, when operating in a first mode, uses data stored in a set of predictor entries to generate predictions. For example, the integrated circuit may be configured to: detect a security domain transition for software being executed by the integrated circuit; responsive to the security domain transition, change a mode of the predictor circuit from the first mode to a second mode and invoke a reset of the set of predictor entries, wherein the second mode prevents the use of a first subset of the predictor entries of the set of predictor entries; and, after completion of the reset, change the mode back to the first mode.

2020018, Jun 11, 2020

Dec 10, 2018

16/215328

- San Mateo CA, US
Andrew Waterman - Berkeley CA, US

G06F 9/30
G06F 9/38

Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

2017001, Jan 19, 2017

Jul 15, 2016

15/211746

Roman Kalukiewicz - San Francisco CA, US
Titia Tin Yee Wong - Oakland CA, US
Petra Cross - San Francisco CA, US
Andrew Waterman - Oakland CA, US
Michael Kuo-Li Ying - San Francisco CA, US
Zachary Cancio - San Francisco CA, US

G06Q 20/32
G06Q 20/20
G06Q 30/02

Processing of merchant-specific functionality services during proximity connection transactions. The merchant terminal transmits additional data to the computing device that enables the device to identify the merchant. The computing device can enable merchant-specific features, such as offers, rewards, loyalty information, and other incentives that are applicable to the identified merchant. The bi-directional communication between the devices permits the computing device to transmit these identified incentives to the merchant terminal. The merchant terminal can then adjust the purchase price. The computing device can also enable a merchant-specific financial instrument and can communicate the identity of the merchant to a management system. The management system can establish a network connection with the merchant to provide larger amounts of data that would otherwise exceed the limited bandwidth of the proximity connection used to establish the secure communication channel between the computing device and the merchant terminal.