Andy R HuangIowa City, IA

8595059, Nov 26, 2013

Oct 12, 2011

13/271284

Andy Huang - Cupertino CA, US

Google Inc. - Mountain View CA

G06Q 30/00

705 141, 705 1423, 705 267

A gift payment management system allows a user to redirect a payment request for selected offers to one or more potential purchasers. The gift payment management system monitors the potential purchaser's response. If the gift payment request is accepted by a potential purchaser, the gift payment management system facilitates verification of payment from the potential purchaser and notifies the user that the gift payment request was accepted. The product associated with the offers is then made available to the user. If multiple purchasers are designated, the gift payment management system further withdraws the gift payment request after the request is completed.

2003020, Nov 6, 2003

May 3, 2002

10/063625

Andy Huang - San Jose CA, US

G06F017/50

703/014000

Technique to improve circuit level simulation speed through the block characterization of the RC network based on the AWE (Asymptotic Waveform Evaluation) is proposed. Since the numbers of RC network of the recent VLSI circuit becomes huge, the complexities of them are the most difficult and time-consuming task in the circuit verification. In addition to the increasing size of the RC networks, the accuracy is another big concern in the circuit simulation and verification. To have the speed while maintaining the accuracy in the circuit simulation, abstraction by block characterization is devised, implemented, and benchmarked. It first extracts transfer equation from the complex RC networks by applying AWE, modeled them as simple -model, then find effective capacitance. The effective capacitance is modeled as pin capacitance of the input of the block, the transfer equation is modeled as a function of the between pins in the block. Converting the RC network into block and computing matrix with block, instead of RC network, can reduce the time to solve the matrix by the two orders of time while keeping the accuracy.

2003020, Nov 6, 2003

May 3, 2002

10/063626

Andy Huang - San Jose CA, US

Mr. Andy Huang, ACAD, Corp. - San Jose CA

G06F017/50

703/014000

A method for modeling junction capacitance of the MOSFET transistor is proposed and implemented for high-speed circuit simulator. A region-based value of the capacitance of MOSFET is proposed, and its regional capacitance value model is more accurate and takes less computation time than the conventional bias independent average capacitance model.

2003020, Nov 6, 2003

May 3, 2002

10/063627

Andy Huang - San Jose CA, US

G06G007/62

703/017000

A method for minimizing event scheduling overhead in VHDL simulation were proposed, and the speed-up of the VHDL simulation time can be obtained. It consists of the two ideas. The first idea excludes any events that do not have any effects on VHDL simulation. The second idea is grouping multiple homogeneous events, and treating them as a single event to reduce the burden of scheduling in the simulation. These idea were applied separately as well as in a combined way.

2003020, Nov 6, 2003

May 3, 2002

10/063624

Andy Huang - San Jose CA, US

ACAD Corp. - San Jose CA

G06F017/50

716/002000, 716/001000, 716/011000, 716/008000

Compacting layout is the process of shrinking the polygons that were devices and wires, and were represented thorough the GDS (general data stream) standard format. To shrink the polygons under the constraints and rules for VLSI design and manufacturing, there is lots of computation time to find optimum width. Especially, the wire is the most complex and takes the most of the time among devices, such as transistors, resistors, and capacitors in the VLSI design. Proposed is the technique to reduce the most computation time in computation of wire length in the shrinking the VLSI layout design. By applying the incremental technique on the shrinking the wire minimization procedure, the performance of the compaction can be improved compared with the technique without incremental one. Wire length minimization process can be formulated by the linear programming, and find optimum solutions by the Simplex[1]. The Simplex is the technique to find global solutions, by applying successive conversion with “pivoting”[1]. The successive conversion procedure is based on the graph theory; set the initial spanning tree, convert it with less cost if any, repeatedly, until there is tree that has minimum cost. The performance can be achieved since the computation to find the cost is performed only on the transformed tree node of the spanning tree

2004014, Jul 29, 2004

Feb 7, 2003

10/248684

Andy Huang - San Jose CA, US

G06F017/10

703/002000

Detecting power and IR-drop is indispensable design process because todays circuits are very power and timing critical. Many approaches provide good solutions for average power consumption and average IR-drop. However, there are few methods in detecting peak power and peak IR-drop. Obviously, peak power and IR-drop are more informative to know real working behavior of a chip than average power and IR-drop. Unfortunately, detection of peak power(current) of a system uses time-consuming process employing normal power calculation for small time regions. This patent suggests a high-speed method with linear complexity for detecting the peak power regions. Once we know peak regions, we can analyze those regions in details.

2005011, Jun 2, 2005

Feb 7, 2003

10/248685

Andy Huang - San Jose CA, US

H04L012/26

370229000

Present invention suggests a method to extract accurate value and time domain of the current in the VLSI circuit, which is almost impossible by the conventional methods. Conventional approaches take the current of a cell as a constant average value extracted by power consumption, which makes designers underestimate peak current and IR-drop of a system. There is no current model considering the cell (or gate) delay and node slew rate even though they are significant factors for the cell current behavior. To re-construct the current waveform efficiently, we divide the cell current into the intrinsic and the output load current. The intrinsic current can be computed with energy value from the power library when the cell becomes active. The load current is computed based on the slew rate, effective start and end time points of the current wave. Instead of using the conventional current information, present invention reconstructs the current information of the design. Due to the accurate current analysis, it has outstanding accuracy to analyze the whole chip precisely in IR drop analysis and peak power analysis.

2013002, Jan 31, 2013

Jul 24, 2012

13/556886

Andy Teh-An Huang - Cupertino CA, US

A61K 36/28
A61P 37/00
A61P 33/02
A61P 31/22
A61P 31/14
A61P 33/04
A61P 31/04
A61P 35/00
A61P 21/00
A61P 11/00
A61P 9/04
A61P 31/06
A61P 5/00
A61P 29/00
A61P 17/00
A61P 11/02
A61P 11/06
A61P 37/08
A61K 9/48
A61P 1/16

424451, 42419515

Compounds having unique properties are prepared from the herbal compositions described herein and comprise extracts derived from plants and fungi of the genera , and . The compositions are useful in preventing, treating, relieving, and improving the quality-of-life of patients suffering from chronic diseases, such as liver diseases, cancer, cachexia, and immune system disorders.