David E Gulbransen, 72Napa, CA

2012015, Jun 21, 2012

Dec 15, 2010

12/968811

Jeffrey F. DeNatale - Thousand Oaks CA, US
David J. Gulbransen - Thousand Oaks CA, US
William E. Tennant - Thousand Oaks CA, US
Alexandros P. Papavasiliou - Thousand Oaks CA, US

H01L 27/146
H01L 31/18

2502081, 438 34, 257E27133, 257E3111

An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

2017019, Jul 6, 2017

Dec 30, 2015

14/985101

- Thousand Oaks CA, US
Jeffrey F. DeNatale - Thousand Oaks CA, US
David J. Gulbransen - Thousand Oaks CA, US
Alan Roll - Oak Park CA, US

H01L 49/02
H01L 27/146
H01L 21/3105
H01L 21/3205
H01L 21/3213
H01L 23/532
H01L 21/306

An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

2016028, Sep 29, 2016

Mar 27, 2015

14/671930

- Thousand Oaks CA, US
David J. Gulbransen - Thousand Oaks CA, US

H03F 1/02
H03F 3/45
H04N 5/3745
H03F 3/08

A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.