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Anthony J Farino, 695909 Camino Placido NE, Albuquerque, NM 87109

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5909 Camino Placido NE, Albuquerque, NM 87109    505-8579238   

Tempe, AZ   

Phoenix, AZ   

Chandler, AZ   

Beaverton, OR   

5909 Camino Placido NE, Albuquerque, NM 87109    505-4943003   

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Anthony John Farino

Address:
5909 Camino Placido NE, Albuquerque, NM 87109
Licenses:
License #: A4168283
Category: Airmen

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Anthony Farino

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Anthony Farino

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Us Patents

Reconditioning Of Semiconductor Substrates To Remove Photoresist During Semiconductor Device Fabrication

US Patent:
6682607, Jan 27, 2004
Filed:
Mar 5, 2002
Appl. No.:
10/092215
Inventors:
Anthony J. Farino - Albuquerque NM
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
B08B 304
US Classification:
134 26, 134 2, 134 32, 134 33, 134 34, 134 36, 134 42, 134902, 510176
Abstract:
A method for reconditioning the surface of a semiconductor substrate to remove an unwanted (i. e. defective) layer of photoresist is disclosed. The method adapts a conventional automated spinner which is used to rotate the substrate at high speed while a stream of a first solvent (e. g. acetone) is used to dissolve the photoresist. A stream of a second solvent (e. g. methanol) is then used to clean the substrate at a lower speed, with the substrate being allowed to dry with continued rotation. The method of the present invention can be used within a photolithography track so that the substrates need never leave the track for reconditioning.

Wafer-Level Packaging With Compression-Controlled Seal Ring Bonding

US Patent:
8575748, Nov 5, 2013
Filed:
Dec 13, 2011
Appl. No.:
13/324076
Inventors:
Anthony J. Farino - Albuquerque NM, US
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
H01L 23/12
US Classification:
257704, 257710, 257E23193, 257E23127, 257E2318, 438125
Abstract:
A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Method For Photolithographic Definition Of Recessed Features On A Semiconductor Wafer Utilizing Auto-Focusing Alignment

US Patent:
5783340, Jul 21, 1998
Filed:
Jul 31, 1997
Appl. No.:
8/903985
Inventors:
Anthony J. Farino - Albuquerque NM
Stephen Montague - Albuquerque NM
Jeffry J. Sniegowski - Albuquerque NM
James H. Smith - Albuquerque NM
Paul J. McWhorter - Albuquerque NM
Assignee:
Sandia Corporation - Albuquerque NM
International Classification:
G01B 1100
G03F 900
US Classification:
430 22
Abstract:
A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface.

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