Anthony L O'Toole, 37Oakland, CA

5870627, Feb 9, 1999

Dec 20, 1995

8/576868

Anthony J.P. O'Toole - San Jose CA
Sriraman Chari - Fremont CA

Cirrus Logic, Inc. - Fremont CA

G06F 1328

395842

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors. No matter in which order the individual channels of the multi-channel system use and return the data buffers, the available descriptors are maintained in contiguous locations in the descriptor queue, increasing the efficiency of the system since searching through the descriptor queue for available descriptors is not required.

4975828, Dec 4, 1990

Aug 5, 1987

7/084717

John Wishneusky - Sunnyvale CA
Cecil Kaplinsky - Palo Alto CA
Anthony O'Toole - San Jose CA
Shahin Hedayat - Pleasanton CA
Shrikant Acharya - Fremont CA

Cirrus Logic, Inc. - Milpitas CA

G06F 300

364200

This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time. The flexibility of this general purpose architecture enables controllers to be more customized to a particular user's requirements, resulting not only in faster performance by the controller itself, but also in far less reliance on the host's processing power.