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Arindam M Chatterjee, 55Cupertino, CA

Arindam Chatterjee Phones & Addresses

Cupertino, CA   

602 Liberty Ct, Ankeny, IA 50021    515-9631141   

1005 Crawford Ct, Ankeny, IA 50021    515-4578766    515-9631141   

4324 Westbrook Dr, Ames, IA 50014    515-2680632   

2160 Grand Ave, West Des Moines, IA 50265   

Ballwin, MO   

Lincoln, NE   

1005 SE Crawford Ct, Ankeny, IA 50021    515-2908068   

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

School / High School: University of Tennessee / Memphis / College of Medicine & Surgery 2005

Languages

English

Emails

Mentions for Arindam M Chatterjee

Career records & work history

Medicine Doctors

Arindam Chatterjee Photo 1

Dr. Arindam R Chatterjee, Saint Louis MO - MD (Doctor of Medicine)

Specialties:
Neuroradiology
Address:
510 S Kingshighway Blvd, Saint Louis, MO 63110
314-3625949 (Phone)
Languages:
English
Education:
Medical School
University of Tennessee / Memphis / College of Medicine & Surgery
Graduated: 2005

Arindam R. Chatterjee

Specialties:
Neuroradiology
Work:
University Medical AssociatesMedical University Of South Carolina Radiology
96 Jonathan Lucas St, Charleston, SC 29425
843-7922396 (phone) 843-7921767 (fax)
Site
Education:
Medical School
University of Tennessee College of Medicine at Memphis
Graduated: 2006
Languages:
English, Italian, Portuguese, Spanish
Description:
Dr. Chatterjee graduated from the University of Tennessee College of Medicine at Memphis in 2006. He works in Charleston, SC and specializes in Neuroradiology. Dr. Chatterjee is affiliated with Medical University Of South Carolina.

Arindam Chatterjee resumes & CV records

Resumes

Arindam Chatterjee Photo 28

Independent Hospital & Health Care Professional

Location:
United States
Industry:
Hospital & Health Care
Arindam Chatterjee Photo 29

Global Head Of Software Engineering

Location:
Cupertino, CA
Industry:
Financial Services
Work:
Ey
Global Head of Software Engineering
Capgemini Consulting 2015 - 2017
Senior Manager, Software Architecture and Delivery
Allstate 2015 - 2017
Director of Architecture
Etherios 2014 - 2015
Director, Technology
Equifax Jan 2013 - Mar 2014
Senior Director of Technology
Edossea May 2009 - Jan 2013
Founder and President
Principal Financial Group Jun 2006 - Apr 2012
Senior Director of Engineering
Wells Fargo Jan 2000 - Jun 2006
Vice President, Technology
Wells Fargo Jul 1995 - Dec 2000
Systems Architect
Education:
Calcutta University, Kolkata 2003 - 2006
Bachelor of Commerce, Bachelors, Commerce, Business
Center For Management Research 2004
Mit Sloan School of Management 2002
University of Iowa
Master of Business Administration, Masters
University of Nebraska - Central Administration System Office
Master of Science, Masters
Institute of Technology
Bachelors
Indian Institute of Technology
The University of Iowa Tippie College of Business
Master of Business Administration, Masters
University of Nebraska - Lincoln
Master of Science, Doctorates, Masters, Doctor of Philosophy
Indian Institute of Technology, Kharagpur
Bachelors, Bachelor of Technology
Skills:
Financial Reporting, Account Reconciliation, Accounts Receivable, Corporate Fp&A, Team Management, Financial Analysis, It Strategy, Technology Management, Cross Functional Team Leadership, Sdlc, Integration, Enterprise Software, Strategy, Software Development, Business Analysis, Product Management, Agile Methodologies, Soa, Leadership, Enterprise Architecture, Start Ups, Architecture, E Commerce, Business Intelligence, Saas, Java Enterprise Edition, Software Project Management, Business Process Improvement, Consulting, Requirements Gathering, Architectures, Data Warehousing, Change Management, Product Development, Solution Architecture, Analysis, Entrepreneurship, Cloud Computing, Vendor Management, Analytics, It Management, Xml, Program Management, Business Strategy, Requirements Analysis, Software Engineering, System Architecture, Business Process, Software Design, Technical Leadership, Executive Management, Management Consulting, Sharepoint, Salesforce.com, Java, Sql
Languages:
English
Bengali
Hindi
Arindam Chatterjee Photo 30

Arindam Chatterjee

Arindam Chatterjee Photo 31

Arindam Chatterjee

Arindam Chatterjee Photo 32

Arindam Chatterjee

Arindam Chatterjee Photo 33

Audit Consultant

Work:

Audit Consultant
Arindam Chatterjee Photo 34

Arindam Chatterjee

Arindam Chatterjee Photo 35

Arindam Chatterjee

Location:
United States

Publications & IP owners

Us Patents

Method And Apparatus For Performing Extraction Using A Model Trained With Bayesian Inference Using A Hybrid Monte Carlo Method

US Patent:
6687887, Feb 3, 2004
Filed:
Jan 31, 2002
Appl. No.:
10/061437
Inventors:
Steven Teig - Menlo Park CA
Arindam Chatterjee - San Carlos CA
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 5, 716 4
Abstract:
A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The system uses Bayesian inference implemented with a hybrid Monte Carlo method to train a set of neural networks for extraction problems.

Method And Apparatus For Performing Extraction Using A Model Trained With Bayesian Inference

US Patent:
6735748, May 11, 2004
Filed:
Jan 31, 2002
Appl. No.:
10/062185
Inventors:
Steven Teig - Menlo Park CA
Arindam Chatterjee - San Carlos CA
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 945
US Classification:
716 5, 716 2, 716 4
Abstract:
A machine-learning model may be created to perform integrated circuit layout extraction. Using such a machine-learning system has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system performs machine learning using Bayesian inference in order to train the neural network models. The Bayesian inference may be implemented with normal Monte Carlo techniques, Hybrid Monte Carlo techniques, or other Bayesian learning techniques. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.

Method And Arrangement For Extracting Capacitance In Integrated Circuits Having Non Manhattan Wiring

US Patent:
6854101, Feb 8, 2005
Filed:
May 9, 2003
Appl. No.:
10/434670
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 5, 716 6, 716 10
Abstract:
The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance effect from the approximated Manhattan wiring section may then be adjusted with a correction factor. Specifically, the present invention proposes that the capacitance be calculated for an interconnect wiring section by multiplying the length of the interconnect wiring section by an approximated capacitance per unit length value of a similar Manhattan wiring segment and adding a correction factor that corrects for the difference between the approximated Manhattan wiring section and the original non Manhattan wiring section.

Method And Apparatus For Performing Extraction Using Machine Learning

US Patent:
6857112, Feb 15, 2005
Filed:
Jan 31, 2002
Appl. No.:
10/062264
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 5, 716 4, 716 6
Abstract:
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The training sets are then used to train the models. In one embodiment, neural networks are used to model the extraction problems.

Method And Apparatus For Creating A Critical Input Space Spanning Set Of Input Points To Train A Machine Learning Model For Extraction

US Patent:
6880138, Apr 12, 2005
Filed:
Dec 31, 2002
Appl. No.:
10/335097
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 4, 716 5, 716 6, 716 1
Abstract:
The present invention introduces novel methods of generating input vectors for machine learning system that will perform extraction. Experimental design is employed to select a set of training points that provide the best information. In one embodiment, a set of input vectors and output vectors are analyzed to determine a set of critical input parameters. Then, a spanning point generation program is used to generate a set of spanning points that cover the identified critical input space. The training point set then used to train a machine learning model.

Method And Apparatus For Creating An Extraction Model Using Bayesian Inference

US Patent:
6883148, Apr 19, 2005
Filed:
Jan 31, 2002
Appl. No.:
10/062193
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F017/50
G06F017/11
G06F017/17
G06F017/18
US Classification:
716 4, 703 2, 703 15, 706920, 706 47
Abstract:
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The system them uses the created training sets to train neural networks that will be used to model the extraction problems. Bayesian inference is used to train the neural networks models.

Method And Apparatus For Performing Extraction Using A Model Trained With Bayesian Inference Via A Monte Carlo Method

US Patent:
6892366, May 10, 2005
Filed:
Jan 31, 2002
Appl. No.:
10/066326
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F009/45
US Classification:
716 5, 716 4, 716 7
Abstract:
A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system uses Bayesian inference implemented with a Monte Carlo method to train a set of neural networks for extraction problems.

Method And Apparatus For Performing Extraction Using A Neural Network

US Patent:
6907591, Jun 14, 2005
Filed:
Jan 31, 2002
Appl. No.:
10/062184
Inventors:
Steven Teig - Menlo Park CA, US
Arindam Chatterjee - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F009/45
US Classification:
716 7
Abstract:
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system trains a set of neural networks using the training sets. In one embodiment, Bayesian inference is used to train the neural networks that are used to model the extraction.

Isbn (Books And Publications)

Finite Element Method For Electromagnetics: Antennas, Microwave Circuits, And Scattering Applications

Author:
Arindam Chatterjee
ISBN #:
0780334256

Public records

Vehicle Records

Arindam Chatterjee

Address:
602 NE Liberty Ct, Ankeny, IA 50021
Phone:
515-9631141
VIN:
5UXFE435X7L011010
Make:
BMW
Model:
X5
Year:
2007

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