Arnold S Berger, 8021706 5Th Pl, Redmond, WA 98074

7089170, Aug 8, 2006

Jul 25, 2001

09/916148

Michael R. Buckmaster - Seattle WA, US
Arnold S. Berger - Redmond WA, US

Freescale Semiconductor, Inc. - Austin TX

G06F 17/50

703 14, 712 1, 703 28

A system for testing an embedded system containing a target processor executing a target program and target hardware that has a physical portion and a simulated portion. A target monitor determines when the target processor is attempting to access simulated hardware. The address bus of the microprocessor is monitored to detect an address in the address space of the simulated hardware. Lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware may also indicate simulation. A bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data.

6298320, Oct 2, 2001

Feb 17, 1998

9/024324

Michael R. Buckmaster - Seattle WA
Arnold S. Berger - Redmond WA

Applied Microsystems Corporation - Redmond WA

G06F 9455

703 28

A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data.

5051888, Sep 24, 1991

Dec 30, 1988

7/292590

John D. Hansen - Colorado Springs CO
Arnold S. Berger - Colorado Springs CO
Lewis S. Kootstra - Colorado Springs CO
Beth V. Jones - Colorado Springs CO
Stan W. Bowlin - Colorado Springs CO
William Fleck - Colorado Springs CO

Hewlett Packard Company

G06F 906
G06F 1516
G06F 9455
G06F 1312

364200

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unsion. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepare to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then goes true.

5202976, Apr 13, 1993

Jun 21, 1991

7/718728

John D. Hansen - Colorado Springs CO
Arnold S. Berger - Colorado Springs CO
Lewis S. Kootstra - Colorado Springs CO
Beth V. Jones - Colorado Springs CO
Stan W. Bowlin - Colorado Springs CO
William Fleck - Colorado Springs CO

Hewlett-Packard Company - Palo Alto CA

G06F 1516
G06F 900
G06F 1130

395500

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unison. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepared to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then does true.