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Kevin D Traylor, 374938 S Drexel Blvd APT 210, Chicago, IL 60615

Kevin Traylor Phones & Addresses

4938 S Drexel Blvd APT 210, Chicago, IL 60615    312-4504883   

Bourbonnais, IL   

Bolingbrook, IL   

Mentions for Kevin D Traylor

Kevin Traylor resumes & CV records

Resumes

Kevin Traylor Photo 37

General Worker

Location:
Chicago, IL
Industry:
Staffing And Recruiting
Work:
Titan Company Limited
General Worker
Kevin Traylor Photo 38

Kevin Traylor

Kevin Traylor Photo 39

Operations Manager

Work:

Operations Manager
Kevin Traylor Photo 40

Country Logistics Manager - Iraq

Work:

Country Logistics Manager - Iraq
Kevin Traylor Photo 41

Kevin Traylor

Kevin Traylor Photo 42

Kevin Traylor

Kevin Traylor Photo 43

Kevin Traylor

Location:
United States

Publications & IP owners

Us Patents

Vco Gain Tracking For Modulation Gain Setting Calibration

US Patent:
6834183, Dec 21, 2004
Filed:
Nov 4, 2002
Appl. No.:
10/287382
Inventors:
Gregory Black - Vernon Hills IL
Daniel B Schwartz - Gold Canyon AZ
Kevin Traylor - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04B 1118
US Classification:
4551821, 4551832, 4551823, 331 17
Abstract:
Voltage controlled oscillator (VCO) gain tracking is used for programming modulation gain settings to minimize modulation distortion in a phase locked loop of a mobile station ( ). A synthesizer ( ) generates a tuning voltage (Vt) for controlling a frequency of a (VCO) modulated radio frequency signal. A controller ( ) outputs a modulation data signal and includes an ADC ( ) for receiving the tuning voltage from the synthesizer ( ) on a VCO feedback loop ( ), a gain control lookup table (LUT) ( ) for storing gain setting calibration data for respective mobile station sub-bands, and a gain setting (DAC) ( ) for outputting a modulation gain control signal to the synthesizer ( ). The modulation gain setting calibration data is calibrated using a one-time or continuous calibration methodlogy during, respectively, a background or normal mode of operation.

Configurable Multi-Mode Modulation System And Transmitter

US Patent:
7539462, May 26, 2009
Filed:
Aug 9, 2005
Appl. No.:
11/199737
Inventors:
David S. Peckham - Barrington Hills IL, US
Richard B. Meador - Austin TX, US
Kevin B. Traylor - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04B 1/02
US Classification:
455 83, 455143
Abstract:
A multi-mode transmitter architecture is configurable for multiple modulation modes using either polar or polar-lite modulation. Multiplexed signal paths and reconfigurable components are controlled for performance in GMSK and EDGE burst modes. Polar-lite EDGE modulation is programmed by setting a multiplexer coupling a first amplitude modulated signal path with a frequency modulated signal path input to a dual-mode power amplifier for amplification of the combined EDGE transmission signal. In full-polar EDGE modulation, amplitude modulated signal is multiplexed into a second amplitude modulated signal path for A/D conversion and comparison with a polar feedback signal coupled from the power amplifier output. The resulting comparison is applied to a power control port of the power amplifier to amplitude modulate the EDGE transmission output. Multiplexers are configured to disconnect the amplitude modulated paths when operating in GMSK signaling for both full-polar and polar-lite modulation.

Error Correcting Viterbi Decoder

US Patent:
8099657, Jan 17, 2012
Filed:
Jul 11, 2008
Appl. No.:
12/218183
Inventors:
Christopher J. Becker - Palatine IL, US
Kevin B. Traylor - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03M 13/03
US Classification:
714795, 714746, 714752, 714758, 714780, 714786, 714792, 714794, 714796, 714807, 375341
Abstract:
Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Error Correcting Viterbi Decoder

US Patent:
8181098, May 15, 2012
Filed:
Jun 11, 2008
Appl. No.:
12/157512
Inventors:
Christopher J. Becker - Palatine IL, US
Kevin B. Traylor - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 11/00
US Classification:
714796, 714792, 714794, 714795
Abstract:
Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.

Optical Clock Signal Distribution

US Patent:
2002018, Dec 5, 2002
Filed:
Jun 1, 2001
Appl. No.:
09/870831
Inventors:
Timothy Johnson - Mundelein IL, US
Kevin Traylor - Haltom City TX, US
Duane Rabe - Hawthorn Woods IL, US
Barbara Barenburg - Gilbert AZ, US
Assignee:
MOTOROLA, INC. - Schaumburg IL
International Classification:
G02B006/12
US Classification:
385/014000, 438/069000
Abstract:
An integrated circuit that distributes its clock signals optically is provided. The integrated circuit may preferably include a plurality of digital CMOS circuits that communicate optically. The optical devices are preferably formed from compound semiconductor structures.

Structure And Method For Fabricating A High-Speed Interface In Semiconductor Structures

US Patent:
2002018, Dec 5, 2002
Filed:
Jun 1, 2001
Appl. No.:
09/870832
Inventors:
Timothy Johnson - Mundelein IL, US
Kevin Traylor - Austin TX, US
Duane Rabe - Hawthorne Woods IL, US
Assignee:
MOTOROLA, INC. - Schaumburg IL
International Classification:
G02B006/13
US Classification:
385/014000
Abstract:
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. In this way, high speed devices can be fabricated along with integral silicon-based circuitry to provide an efficient, low-cost semiconductor structure. Moreover, I/O pins and their associated problems can be eliminated.

Optically-Communicating Integrated Circuits

US Patent:
2002018, Dec 5, 2002
Filed:
Jun 1, 2001
Appl. No.:
09/870836
Inventors:
Timothy Johnson - Mundelein IL, US
Kevin Traylor - Austin TX, US
William Ooms - Prescott AZ, US
Assignee:
MOTOROLA, INC. - Schaumburg IL
International Classification:
G02B006/12
US Classification:
385/014000
Abstract:
A system of integrated circuits including a plurality of optical semiconductor devices formed in silicon substrates such that the devices optically communicate with one another. The optical semiconductor devices are preferably formed from compound semiconductor structures. Each substrate may be formed in a single plane.

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