Balwinder S Singh, 67Austell, GA

2006000, Jan 5, 2006

Nov 15, 2003

10/535557

Klaas-Jan De Langen - Sunnyvale CA, US
Balwinder Singh - Union City CA, US
Edmond Toy - Sunnyvale CA, US

Koninklijke Philips Electronics N.V. - BA Eindhoven

H03K 19/0175

326080000

A level shifting circuit () couples an input current (Iin) from one system to another, isolated, system, by driving a single load (L) via one or more current mirrors of a common type. In a first embodiment (), two similar type (either N-type or P-type) current mirrors (M,M;M,M) provide output current (Iout, Iout) to a common load. Diodes (D,D) are used to split the input current (Iin, Iin) between the two current mirrors during normal, non-faulty conditions, and to turn off either one of the two current mirrors during a fault condition to permit proper operation in the presence of a fault. In a second embodiment (), a single current mirror (M,M) mirrors the input current (Iin) to the output load (L), and a pair of diodes (D,D) selects which of the isolated systems to use as the power source in the event of a fault.

6452418, Sep 17, 2002

Jun 28, 2001

09/894390

Balwinder Singh - Union City CA
Klaas-Jan De Langen - Sunnyvale CA
Martijn Bredius - San Jose CA

Koninklijke Philips Electronics N.V. - Eindhoven

H03K 19084

326 68, 326 81, 326 83

A driving circuit provides a symmetric differential driving signal relative to one set of voltage potentials to a driver circuit that drives an output node to another set of voltage potentials. The differential driving signals from the driving system are equal and opposite to each other, thereby avoiding stray current flow between the driving system and the driven current mirrors. The transistors that provide the driving signal are continuously biased, using a weak bias in one logic state and stronger bias in the other state, to avoid hard-switching transients.

2020009, Mar 26, 2020

Sep 24, 2018

16/140356

- Santa Clara CA, US
Balwinder Singh - Union City CA, US
Gerald R. Talbot - Concord MA, US
Alushulla Jack Ambundo - Austin TX, US
Edoardo Prete - Arlington MA, US
Michael A. Margules - Austin TX, US

G11C 5/14
H03K 17/687
H04L 25/02
G11C 11/4074

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.