Barbara C Vasquez, 80Sparks, NV

6714418, Mar 30, 2004

Nov 1, 2002

10/285924

Gerd Frankowsky - Hoehenkirchen-Siegertsbrunn, DE
Harry Hedler - Germering, DE
Roland Irsigler - Munich, DE
Thorsten Meyer - Dresden, DE
Barbara Vasquez - Orinda CA

Infineon Technologies AG - Munich

H05K 702

361735, 361728, 361729, 361784, 361790, 257686

An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection. Subsequently, each of the components, which comprise a stack of chips, is separated from the assembled stack of chip arrangements.

6905954, Jun 14, 2005

Aug 5, 2003

10/634242

Harry Hedler - Germering, DE
Thorsten Meyer - Dresden, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01L021/44

438612, 438613, 257779, 257780

The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level () to a semiconductor substrate (); structuring the interconnect level (); and applying a solder layer () on the structured interconnect level () in such a way that the solder layer () assumes the structure of the interconnect level (). The present invention likewise provides such a semiconductor device.

6916185, Jul 12, 2005

Jun 18, 2003

10/464429

Harry Hedler - Germering, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01R012/00
H05K001/00

439 83

The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by performing the steps of: providing a main area (HF) of the integrated circuit (), which has an electrical contacting region (), with a mechanical supporting structure (); providing a solderable surface region () of the mechanical supporting structure (); providing a solderable terminal region (), which is electrically connected to the electrical contacting region (), on the main area (HF) of the integrated circuit (); providing a main area (HF) of the substrate () with a first soldering region (), which can be aligned with the solderable surface regions (), and with a second soldering region (), which can be aligned with the solderable terminal region (); and simultaneous soldering of the surface regions () to the first soldering region () and of the terminal region () to the second soldering region ().

6919232, Jul 19, 2005

Oct 31, 2002

10/284649

Harry Hedler - Germering, DE
Roland Irsigler - Munich, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01L021/44
H01L021/48
H01L021/50

438127, 438124, 438126

A process for producing a semiconductor chip having contact elements protruding on one chip side within the context of wafer level packaging, the chip side provided with the contact elements being coated with a covering compound forming a protective layer, from which the protruding contact element project.

6953708, Oct 11, 2005

Aug 15, 2003

10/642063

Harry Hedler - Germering, DE
Thorsten Meyer - Dresden, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01L021/48

438110, 438126

A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.

7074696, Jul 11, 2006

Jul 29, 2003

10/630632

Gerd Frankowsky - Höhenkirchen-Siegertsbrunn, DE
Harry Hedler - Germering, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01L 21/00
H01L 21/44
H01L 21/46

438464, 438 67, 438 68, 438107, 438455, 438458

The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

7087512, Aug 8, 2006

Aug 15, 2003

10/642092

Harry Hedler - Germering, DE
Roland Irsigler - Munich, DE
Thorsten Meyer - Dresden, DE
Barbara Vasquez - Orinda CA, US

Infineon Technologies AG - Munich

H01L 21/44

438612, 438613

A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

7176131, Feb 13, 2007

Oct 12, 2004

10/960994

Georg Meyer-Berg - München, DE
Barbara Vasquez - Lafayette CA, US

Infineon Technologies AG - Munich

H01L 21/44

438675, 257778, 257E21575, 438584, 438614, 438617, 438524, 438666

An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.