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Benjamin V Fasano, 71Wall Township, NJ

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Neptune, NJ   

Woodbine, NJ   

Asbury Park, NJ   

30 Windy Hill Rd, New Windsor, NY 12553    845-4962938   

11 Ryan Ct, New Windsor, NY 12553   

Newburgh, NY   

94 Park Ave, Edison, NJ 08817    732-8190612   

30 Windy Hill Rd, New Windsor, NY 12553   

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Benjamin V Fasano

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Work

Company: Globalfoundries Position: Engineer

Education

Degree: High school graduate or higher

Skills

Engineering • Manufacturing • Semiconductors • Electronics • Testing • Microsoft Office • C • Matlab • Project Management • C++ • Photonics • Elecronics Packaging

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Industries

Semiconductors

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Benjamin Fasano resumes & CV records

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Benjamin Fasano Photo 14

Engineer

Location:
1207 Grand Ave, Asbury Park, NJ 07712
Industry:
Semiconductors
Work:
Globalfoundries
Engineer
Skills:
Engineering, Manufacturing, Semiconductors, Electronics, Testing, Microsoft Office, C, Matlab, Project Management, C++, Photonics, Elecronics Packaging

Publications & IP owners

Us Patents

Land Grid Array Alignment And Engagement Design

US Patent:
6354844, Mar 12, 2002
Filed:
Dec 13, 1999
Appl. No.:
09/459552
Inventors:
Patrick A. Coico - Fishkill NY
Benjamin V. Fasano - New Windsor NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 1200
US Classification:
439 66, 439 74, 439260, 439525
Abstract:
A Land Grid Array electronic package having an array of contact pads is connected to a corresponding array of contact pads on a circuit board through a matching array of conductive pins of a flexible interposer. Alignment of the electronic package to the flexible interposer and flexible interposer to the circuit board is obtained by registration of alignment components to the contact pads and conductive pins. A pair of alignment components, such as pin-like alignment structures, on selected pads of both the electronic package and circuit board mate within alignment holes at the sites of corresponding pin locations in said flexible interposer. Alternatively, the pin-like alignment structures on the electronic package can be extended to pass through the said alignment holes of said flexible interposer into alignment holes which replace the pin-like alignment structure on said circuit board.

Embedded Structures To Provide Electrical Testing For Via To Via And Interface Layer Alignment As Well As For Conductive Interface Electrical Integrity In Multilayer Devices

US Patent:
6391669, May 21, 2002
Filed:
Jun 21, 2000
Appl. No.:
09/598426
Inventors:
Benjamin V. Fasano - New Windsor NY
Hai P. Longworth - Poughkeepsie NY
Anthony L. Plachy - Crompond NY
Robert N. Wiggin - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3104
US Classification:
438 18, 29593
Abstract:
Multilayer substrates, are fabricated with the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, there are provided embedded structures in multilayer substrates, such as are employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.

Method And Structure To Increase Reliability Of Input/Output Connections In Electrical Devices

US Patent:
6407927, Jun 18, 2002
Filed:
Aug 31, 1999
Appl. No.:
09/387325
Inventors:
Benjamin V. Fasano - New Windsor NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 702
US Classification:
361760, 361743, 361719, 361762, 439591, 439 66
Abstract:
A method and connecting structure includes a first surface and a connection pad on said first surface, wherein, said first surface includes an opening adjacent to said connection pad, and wherein, upon sufficient stress, said opening forms a flap allowing a portion of said connection pad to separate from said first surface.

Low Loss Glass Ceramic Composition With Modifiable Dielectric Constant

US Patent:
6436332, Aug 20, 2002
Filed:
Nov 2, 2000
Appl. No.:
09/705139
Inventors:
Benjamin V. Fasano - New Windsor NY
Robert A. Rita - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C04B 35195
US Classification:
264619, 264614, 264650, 264670, 264681, 501 63, 501 66, 501 69, 501 72, 419 19
Abstract:
The dielectric constant of low loss tangent glass-ceramic compositions, such as cordierite-based glass ceramics, is modified over a range by selective addition of high dielectric constant ceramics, such as titanates, tantalates and carbides and metals, such as copper. The low loss tangent is retained or improved over a range of frequencies, and the low CTE of the glass-ceramic is maintained. BaTiO , SrTiO and Ta O produce the most effective results.

Optical Color Tracer Indentifier In Metal Paste That Bleed To Greensheet

US Patent:
6521355, Feb 18, 2003
Filed:
Sep 6, 2000
Appl. No.:
09/656089
Inventors:
Benjamin V. Fasano - New Windsor NY
James N. Humenik - Lagrangeville NY
David C. Long - Wappingers Falls NY
Cynthia J. Calli - Newburgh NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B21D 3900
US Classification:
428621, 428620, 428624, 427 96
Abstract:
A coating material used in the fabrication of electronic components such as a metallized paste is provided comprising a material to be coated on the electronic component substrate and an identifying component which identifying component can be identified and which identifying component identifies the coating material. Optical dyes visible to the eye can be used as the identifying component with a preferred dye being a UV fluorescent dye which is colorless under visible light and visible under UV light. A process for making an electronic component using the coating materials of the invention and electronic components made using the coating material are also provided.

Method And Apparatus For Interim Assembly Electrical Testing Of Circuit Boards

US Patent:
6552529, Apr 22, 2003
Filed:
Dec 17, 2001
Appl. No.:
10/022270
Inventors:
Benjamin V. Fasano - New Windsor NY
Mark G. Courtney - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 2708
US Classification:
3241581, 324715, 438 12
Abstract:
A method and a structure for assembling a circuit board whereby high temperature attach devices can be electrically tested prior to the joining of permanent low temperature attach devices. A test interposer, with low temperature attach known good reference devices, is placed in electrical contact with the circuit board containing high temperature attach devices. The test interposer/circuit board assembly can be used to identify any defective high temperature attach devices which can be replaced prior to joining the permanent low temperature attach devices on the circuit board. This partial interim test, when only the high temperature attach devices are mounted on the circuit board, eliminates the need to remove known good low temperature attach devices from the circuit board during the high temperature attach device rework process.

Stress Resistant Land Grid Array (Lga) Module And Method Of Forming The Same

US Patent:
6703560, Mar 9, 2004
Filed:
Apr 19, 2001
Appl. No.:
09/838454
Inventors:
Patrick Anthony Coico - Fishkill NY
James H. Covell - Poughkeepsie NY
Benjamin V. Fasano - New Windsor NY
Lewis S. Goldman - Bedford NY
Ronald L. Hering - Pleasant Valley NY
Sundar M. Kamath - San Jose CA
Kenneth Charles Marston - Wappingers Falls NY
Frank Louis Pompeo - Redding CT
Karl J. Puttlitz - Wappingers Falls NY
Jeffrey Allen Zitz - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2302
US Classification:
174 524, 257704
Abstract:
An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.

Method To Produce Pedestal Features In Constrained Sintered Substrates

US Patent:
6835260, Dec 28, 2004
Filed:
Oct 4, 2002
Appl. No.:
10/265516
Inventors:
Benjamin V. Fasano - New Windsor NY
David H. Gabriels - Cold Spring NY
Richard F. Indyk - Wappingers Falls NY
Glenn A. Pomerantz - Kerhonkson NY
Richard A. Shelleman - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B32B 3118
US Classification:
156 8911, 156 8912, 156 8916, 156268, 156289
Abstract:
Methods to create raised pedestal parts in ceramic substrates sintered under a load. The invention uses a patterned, buried, non-sintering layer that provides the needed transfer of load during the sintering process to the raised or pedestal portion of the substrate while maintaining dimensional control of the metallized features on the surface of the pedestal base. The methods involve cutting channels in the ceramic substrate corresponding in position to the perimeter of the opening in the patterned non-sintering contact sheet. The channels may be cut either before or after the sintering of the ceramic substrates.

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