Benjamin K Felder, 644011 Avienda Del Sol, Lake Havasu City, AZ 86406

6580383, Jun 17, 2003

Nov 1, 2000

09/703646

Don C. Devendorf - Carlsbad CA
Benjamin Felder - Saugus CA
Lloyd F. Linder - Agoura Hills CA

Telasic Communications, Inc. - El Sequndo CA

H03M 300

341143, 341118, 341120, 341155, 327116

A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution. The method for producing this result includes providing the baseline device having a selected dynamic range at a baseline clock rate; generating the baseline clock rate by translating a reference clock upward by a selected factor; decimating the data rate of the baseline device to a slower data rate so as to achieve a selected degree of oversampling; and producing an output data rate as a sub-multiple of the baseline clock rate with the selected output resolution at the slower data rate. The architecture includes a monolithic substrate on which the baseline ADC provides a dynamic range necessary to satisfy the performance requirements of the final ADC.

6683904, Jan 27, 2004

May 13, 2002

10/144329

Louis F. Linder - Agoura Hills CA
Benjamin Felder - Saugus CA
Don C. Devendorf - Carlsbad CA

Telasic Communications, Inc. - El Segundo CA

H04B 1500

375139

An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signals chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal. Once the chirp rate is detected, the low power LO generator is powered down, the passband of the active bandpass filter is narrowed, and the remaining receiver circuitry is powered up to dechirp the RF input signal.

6882294, Apr 19, 2005

Aug 6, 2003

10/635826

Lloyd F. Linder - Agoura Hills CA, US
Benjamin Felder - Rancho Palos Verdes CA, US

TelASIC Communications, Inc. - El Segundo CA

H03M001/78
H03M001/36

341154, 341156

A subranging analog to digital converter (ADC). The ADC () includes a novel resistive ladder () for a differential quantizer () and a novel summing node circuit (). The novel resistive ladder () includes an input terminal (), a plurality of serially connected resistors R coupled to the input terminal (), and a pair of complementary current sources (and ) for maintaining a constant current flow through the ladder (). The novel summing node circuit () includes an input terminal () for receiving an input signal, a pair of complementary DACs (and ) for generating a reconstruction signal, and a summing amplifier () for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC. The novel method () includes the steps of trimming the complementary current sources of the coarse quantizer to match each other (), trimming each of the DAC cells on one of the complementary DACs (), trimming the overall DAC gain to match the gain of the coarse quantizer (); and trimming the gain of the fine quantizer to match one coarse quantization Q level ().

7098834, Aug 29, 2006

Oct 20, 2004

10/969283

Lloyd F. Linder - Agoura Hills CA, US
Michael F. Clingempeel - Herndon VA, US
William W. Cheng - Redondo Beach CA, US
William J. Rinard - Annapolis MD, US
Benjamin Felder - Saugus CA, US

Raytheon Company - Waltham MA

H03M 1/12
H03M 3/00
H03M 1/44

341155, 341162, 341143

A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

2005003, Feb 17, 2005

May 17, 2004

10/847433

Don Devendorf - Carlsbad CA, US
Benjamin Felder - Rancho Palos Verdes CA, US
Erick Hirata - Torrance CA, US
Christopher Langit - Gardena CA, US
Lloyd Linder - Agoura Hills CA, US

G06G007/00

708801000

A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.

5315169, May 24, 1994

Jun 8, 1992

7/894980

Lloyd F. Linder - Agoura Hills CA
Benjamin Felder - Saugus CA
Dwight D. Birdsall - Norwalk CA

Hughes Aircraft Company - Los Angeles CA

H03K 524
H03K 1774

307353

A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes. The transistors are all bipolar and of the same conductivity type, preferably NPN.

5266952, Nov 30, 1993

Mar 30, 1992

7/860528

Wade J. Stone - Topanga CA
Howard S. Nussbaum - Los Angeles CA
Kikuo Ichiroku - Santa Monica CA
Benjamin Felder - Saugus CA
William P. Posey - Playa Del Rey CA

Hughes Aircraft Company - Los Angeles CA

H03M 112
H03M 304

341156

A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets.

5859569, Jan 12, 1999

Apr 14, 1997

8/843200

Hieu M. Le - Midway City CA
Lloyd F. Linder - Agoura Hills CA
Erick M. Hirata - Torrance CA
Benjamin Felder - Saugus CA
Roger N. Kosaka - Torrance CA
Donald G. McMullin - Rancho Santa Margarita CA
Kelvin T. Tran - Carson CA

Raytheon Company - El Segundo CA

H02H 720
H03M 112

330298

A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.