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Beth R Cook, 495788 S Hakkasan Ave, Boise, ID 83716

Known as:
Beth Rose Cook Beth B Cook Beth Rose Lore Beth R Lore

Beth Cook Phones & Addresses

Boise, ID   

935 Crest Wood Dr, Meridian, ID 83642    208-8840029   

Norristown, PA   

Work

Company: Sungard data systems inc. Address: 680 E Swedesford Rd, Wayne, PA 19087 Phones: 484-5822000 Position: Internet marketing manager Industries: Computer Processing and Data Preparation and Processing Services
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Career records & work history

Lawyers & Attorneys

Beth Cook Photo 1

Beth Cook - Lawyer

Office:
Keating Law Group PC
Specialties:
Torts, Insurance, General Practice
ISLN:
920629572
Admitted:
2006
University:
University of Dayton, B.A., 1995
Law School:
University of Dayton, J.D., 1998

Medicine Doctors

Beth A. Cook

Specialties:
Obstetrics & Gynecology
Work:
Womens Health Partners
75 Springview Ln, Summerville, SC 29485
843-8325096 (phone) 843-8325115 (fax)
Education:
Medical School
West Virginia University School of Medicine
Graduated: 1998
Procedures:
Vaccine Administration, Vaginal Repair, Cesarean Section (C-Section), Colposcopy, Cystoscopy, D & C Dilation and Curettage, Delivery After Previous Caesarean Section, Destruction of Benign/Premalignant Skin Lesions, Hysterectomy, Myomectomy, Ovarian Surgery, Skin Tags Removal, Tubal Surgery, Vaginal Delivery
Conditions:
Candidiasis of Vulva and Vagina, Endometriosis, Female Infertility, Herpes Genitalis, Hypertension (HTN), Menopausal and Postmenopausal Disorders, Polycystic Ovarian Syndrome (PCOS), Premenstrual Syndrome (PMS), Spontaneous Abortion, Abnormal Vaginal Bleeding, Breast Disorders, Complicating Pregnancy or Childbirth, Conditions of Pregnancy and Delivery, Diabetes Mellitus Complicating Pregnancy or Birth, Follicular Cyst of the Ovary, Genital HPV, Gonorrhea, Hemorrhoids, Ovarian Dysfunction, Pelvic Inflammatory Disease (PID), Pregnancy-Induced Hypertension, Uncomplicated or Low Risk Pregnancy and Delivery, Uterine Leiomyoma, Vitamin D Deficiency
Languages:
English
Description:
Dr. Cook graduated from the West Virginia University School of Medicine in 1998. She works in Summerville, SC and specializes in Obstetrics & Gynecology. Dr. Cook is affiliated with Summerville Medical Center.

License Records

Beth A Cook

Licenses:
License #: 23336 - Expired
Category: Nursing Support
Issued Date: Jul 1, 1993
Effective Date: May 28, 1998
Type: Nurse Aide

Beth A Cook

Licenses:
License #: 2090392 - Expired
Category: Health Care
Issued Date: Feb 26, 1990
Effective Date: May 28, 2003
Expiration Date: Apr 30, 2001
Type: Registered Nurse

Publications & IP owners

Us Patents

Filamentary Memory Devices And Methods

US Patent:
2013032, Dec 12, 2013
Filed:
Jun 7, 2012
Appl. No.:
13/491116
Inventors:
Lei Bi - Boise ID, US
Beth R. Cook - Meridian ID, US
Marko Milojevic - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
International Classification:
G11C 11/00
H01L 21/8239
H01L 45/00
US Classification:
365148, 257 2, 438381, 257E45002, 257E21645
Abstract:
Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices are described, so that the logical state of a memory cell that includes the that includes the removable filament can be detected. Additional apparatus, systems, and methods are described.

Resistive Memory Devices

US Patent:
2014006, Mar 6, 2014
Filed:
Aug 30, 2012
Appl. No.:
13/599865
Inventors:
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Lei Bi - Boise ID, US
Beth R. Cook - Meridian ID, US
Dale W. Collins - Boise ID, US
International Classification:
H01L 21/02
H01L 47/00
US Classification:
257 4, 438382, 257E47001, 257E21004
Abstract:
Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.

Methods Of Forming A Memory Cell Having Programmable Material That Comprises A Multivalent Metal Oxide Portion And An Oxygen Containing Dielectric Portion

US Patent:
8633084, Jan 21, 2014
Filed:
Oct 17, 2012
Appl. No.:
13/654258
Inventors:
Beth R. Cook - Meridian ID, US
Lei Bi - Boise ID, US
Wayne Huang - Boise ID, US
Ian C. Laboriante - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/20
US Classification:
438381, 257E21396
Abstract:
A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

Methods Of Incorporating Leaker Devices Into Capacitor Configurations To Reduce Cell Disturb, And Capacitor Configurations Incorporating Leaker Devices

US Patent:
2022036, Nov 17, 2022
Filed:
Jul 14, 2022
Appl. No.:
17/865242
Inventors:
- Boise ID, US
Beth R. Cook - Boise ID, US
Manuj Nahar - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01G 4/38
H01L 27/11507
G11C 11/22
H01L 49/02
Abstract:
Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

Methods Of Forming Structures Containing Leaker-Devices And Memory Configurations Incorporating Leaker-Devices

US Patent:
2022019, Jun 23, 2022
Filed:
Mar 11, 2022
Appl. No.:
17/693035
Inventors:
- Boise ID, US
Beth R. Cook - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Ashonita A. Chavan - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11509
H01G 4/008
H01G 4/06
H01G 4/40
H01L 49/02
H01L 27/11504
G11C 11/22
H01L 27/11507
Abstract:
Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

Semiconductor Devices Including Ferroelectric Materials

US Patent:
2021031, Oct 7, 2021
Filed:
Jun 14, 2021
Appl. No.:
17/347412
Inventors:
- Boise ID, US
Matthew N. Rocklein - Boise ID, US
Beth R. Cook - Meridian ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11507
H01L 49/02
H01L 45/00
Abstract:
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Methods Of Incorporating Leaker-Devices Into Capacitor Configurations To Reduce Cell Disturb, And Capacitor Configurations Incorporating Leaker-Devices

US Patent:
2021013, May 6, 2021
Filed:
Dec 22, 2020
Appl. No.:
17/131065
Inventors:
- Boise ID, US
Beth R. Cook - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Ashonita A. Chavan - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11509
H01G 4/008
H01G 4/06
H01G 4/40
H01L 49/02
H01L 27/11504
G11C 11/22
H01L 27/11507
Abstract:
Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

Memory Cells Comprising Ferroelectric Material And Including Current Leakage Paths Having Different Total Resistances

US Patent:
2021010, Apr 8, 2021
Filed:
Dec 17, 2020
Appl. No.:
17/125030
Inventors:
- Boise ID, US
Beth R. Cook - Boise ID, US
Durai Vishak Nirmal Ramaswamy - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 49/02
H01L 27/11507
Abstract:
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

Possible Relatives

Cynthia Cook  David W Cook  Cyril B Cook  Dawn B Cook  Dawson D Cook  Dayna R Cook  Dean N Cook  Beth Johnson  Beth B Standley  Beth L Stanek 

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