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Bindu Gupta, 64Perth Amboy, NJ

Bindu Gupta Phones & Addresses

Fords, NJ   

Franklin Park, NJ   

Parlin, NJ   

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Bindu Gupta resumes & CV records

Resumes

Bindu Gupta Photo 25

Executive Assistant At Barclays Capital

Position:
Executive Assistant at Barclays Capital
Location:
Greater New York City Area
Industry:
Investment Banking
Work:
Barclays Capital
Executive Assistant
Bindu Gupta Photo 26

Bindu Gupta

Location:
Greater New York City Area
Industry:
Executive Office
Bindu Gupta Photo 27

Executive Assistant At Barclays Capital

Position:
Executive Assistant at Barclays Capital
Location:
Greater New York City Area
Industry:
Investment Banking
Work:
Barclays Capital
Executive Assistant
Dow Jones - New York, NY Dec 2006 - Jul 2007
Executive Assistant
Education:
Punjab University 1981 - 1985
Bachelors, Arts
Bindu Gupta Photo 28

Executive Assistant At Lehman Brothers

Position:
Executive Assistant at Lehman Brothers
Location:
Greater New York City Area
Industry:
Investment Banking
Work:
Lehman Brothers
Executive Assistant
Education:
Panjab University

Publications & IP owners

Us Patents

System And Method For Suppression Of Rfi Interference

US Patent:
7072617, Jul 4, 2006
Filed:
May 19, 2004
Appl. No.:
10/850307
Inventors:
Bindu Gupta - North Brunswick NJ, US
Faramarz Sabouri - Lawrenceville NJ, US
Vladimir Friedman - Scotch Plains NJ, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H04B 1/10
US Classification:
455 63, 330149
Abstract:
A system and method for suppressing RFI receives a differential input signal V, and a signal Vwhich varies with the common mode component of V. Vis phase-shifted and then amplified with a programmable gain G to produce an output V. A subtractor produces an output Vwhich varies with V−V. Vis amplified with a programmable gain G to produce an output V. An analog input signal processing circuit receives Vat an input which has an associated maximum dynamic range. A processor adjusts G such that Vcovers the maximum dynamic range, adjusts the phase shift and G to minimize V, and adjusts G to increase Vsuch that it again covers the maximum dynamic range. The RFI in Vis substantially subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving V.

Jfet Switch Select Circuit

US Patent:
7015683, Mar 21, 2006
Filed:
Oct 20, 2004
Appl. No.:
10/969622
Inventors:
Ojas M. Choksi - Monmouth Junction NJ, US
Bindu Gupta - Monmouth Junction NJ, US
Faramarz Sabouri - Lawrenceville NJ, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G05F 3/16
US Classification:
323313, 323314
Abstract:
A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.

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