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Bogdan I Georgescu, 544675 Seton Hall Rd, Colorado Springs, CO 80918

Known as:
Bogdan J Georgescu Bogda Georgescu Bogdah Gerogescu Georgescu Bogda

Bogdan Georgescu Phones & Addresses

4675 Seton Hall Rd, Colorado Spgs, CO 80918    719-5480871   

5423 Wells Fargo Dr, Colorado Spgs, CO 80918    719-5480871   

Colorado Springs, CO   

4675 Seton Hall Rd, Colorado Springs, CO 80918   

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Position: Sales Occupations

Education

Degree: Bachelor's degree or higher
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Publications & IP owners

Us Patents

Architecture, Method (S) And Circuitry For Low Power Memories

US Patent:
6493283, Dec 10, 2002
Filed:
Nov 22, 2000
Appl. No.:
09/721324
Inventors:
Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 800
US Classification:
36523003, 365 63, 36523005
Abstract:
A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

Block Redundancy In Ultra Low Power Memory Circuits

US Patent:
6535437, Mar 18, 2003
Filed:
Jun 15, 2001
Appl. No.:
09/882898
Inventors:
John J. Silver - Monument CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
Danny L. Rose - Monument CO
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 700
US Classification:
365200, 365226, 365227
Abstract:
A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) one or more control signals. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of one or more of the enable signals generally reduces current consumption in the memory array.

Architecture, Method(S) And Circuitry For Low Power Memories

US Patent:
6674682, Jan 6, 2004
Filed:
Jul 19, 2002
Appl. No.:
10/199560
Inventors:
Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 800
US Classification:
36523003, 365226
Abstract:
A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9. 43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2. 38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0. 91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0. 94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0. 61 mA.

Method And Circuit For High Speed Transmission Gate Logic

US Patent:
7053662, May 30, 2006
Filed:
Feb 13, 2004
Appl. No.:
10/778504
Inventors:
John Silver - Monument CO, US
Bogdan Georgescu - Colorado Springs CO, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 19/20
US Classification:
326113, 326119
Abstract:
A transmission gate logic circuit () can include a supply path () connected to an output of a passgate (). A boost path () can be situated between an input of passgate () and the supply path () and can enable a first supply device (-) within the supply path () in response to a signal C at the input of passgate (). A supply path () can thus provide a boost at the output node () of passgate () resulting in faster logic transition times.

Low Power Bandgap Reference Circuit With Increased Accuracy And Reduced Area Consumption

US Patent:
7683701, Mar 23, 2010
Filed:
Dec 29, 2005
Appl. No.:
11/321854
Inventors:
Bogdan I. Georgescu - Colorado Springs CO, US
Iulian C. Gradinariu - Colorado Springs CO, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G05F 3/16
US Classification:
327539, 323316
Abstract:
Bandgap reference (BGR) circuits and methods are described herein for providing high accuracy, low power Bandgap operation when using small, low voltage devices in the analog blocks of the BGR circuit. In some cases, chopped input stabilization and dynamic current matching techniques may be combined to compensate for input voltage offsets in the operational amplifier portion and current offsets in the current mirror portion of the Bandgap circuit. When used together, the chopped stabilization and dynamic current matching techniques provide a significant increase in accuracy, especially when using small, low voltage devices in the analog blocks to reduce layout area and support low power supply operation (e. g. , power supply values down to about 1. 4 volts and below).

Memory Architecture Having A Reference Current Generator That Provides Two Reference Currents

US Patent:
7969804, Jun 28, 2011
Filed:
Dec 24, 2008
Appl. No.:
12/343617
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 7/00
US Classification:
365206, 365207, 365208, 36518906, 365210
Abstract:
A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

Memory Architecture Having Two Independently Controlled Voltage Pumps

US Patent:
8125835, Feb 28, 2012
Filed:
Dec 24, 2008
Appl. No.:
12/343658
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Raghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan I. Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 16/06
G11C 5/14
US Classification:
36518529, 36518518, 365126
Abstract:
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Memory Architecture Having Two Independently Controlled Voltage Pumps

US Patent:
8542541, Sep 24, 2013
Filed:
Feb 28, 2012
Appl. No.:
13/407660
Inventors:
Ryan T. Hirose - Colorado Springs CO, US
Fredrick Jenne - Sunnyvale CA, US
Vijay Srinivasaraghavan - Colorado Springs CO, US
Igor G. Kouznetsov - San Jose CA, US
Paul Fredrick Ruths - Woodland Park CO, US
Cristinel Zonte - Colorado Springs CO, US
Bogdan Georgescu - Colorado Springs CO, US
Leonard Vasile Gitlan - Colorado Springs CO, US
James Paul Myers - Woodinville WA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 16/04
US Classification:
36518529, 36518518
Abstract:
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Public records

Vehicle Records

Bogdan Georgescu

Address:
4675 Seton Hall Rd, Colorado Spgs, CO 80918
Phone:
719-5480871
VIN:
4T3BK11A39U008165
Make:
TOYOTA
Model:
VENZA
Year:
2009

Possible Relatives

Daniela Georgescu  Dumitru J Georgescu  Florin Georgescu  Gabriel Georgescu  George Georgescu  Lucian Georgescu  Maria A Georgescu  Bogdan Malinowski  Bogdan M Truszkowski  Bogdan N Nowakowski 

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